MC908JL3ECPE Datasheet, PDF (80/180 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor ROM (MON)
V_DD
RST
PTB0
4096 + 32 OSCXCLK CYCLES
24 BUS CYCLES
FROM HOST
FROM MCU
1
4
1
1
2
4
1
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 7-7. Monitor Mode Entry Timing
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a Flash location returns an invalid value and trying to execute code from Flash causes an illegal
address reset. After receiving the eight security bytes from the host, the MCU transmits a break character,
signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is
set. If it is, then the correct security code has been entered and Flash can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the Flash module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
MC68HC908JL3E Family Data Sheet, Rev. 4
80
Freescale Semiconductor