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MC9S08RC8 Datasheet, PDF (90/234 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
Field
7
V
4
H
3
I
2
N
1
Z
0
C
Table 7-1. CCR Register Field Descriptions
Description
Twoâs Complement Overï¬ow Flag â The CPU sets the overï¬ow ï¬ag when a twoâs complement overï¬ow occurs.
The signed branch instructions BGT, BGE, BLE, and BLT use the overï¬ow ï¬ag.
0 No overï¬ow
1 Overï¬ow
Half-Carry Flag â The CPU sets the half-carry ï¬ag when a carry occurs between accumulator bits 3 and 4 during
an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry ï¬ag is required for binary-coded
decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
Interrupt Mask Bit â When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the ï¬rst instruction of the interrupt service
routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening
interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled
Negative Flag â The CPU sets the negative ï¬ag when an arithmetic operation, logic operation, or data
manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most signiï¬cant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result
Zero Flag â The CPU sets the zero ï¬ag when an arithmetic operation, logic operation, or data manipulation
produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the
loaded or stored value was all 0s.
0 Non-zero result
1 Zero result
Carry/Borrow Flag â The CPU sets the carry/borrow ï¬ag when an addition operation produces a carry out of bit
7 of the accumulator or when a subtraction operation requires a borrow. Some instructions â such as bit test and
branch, shift, and rotate â also clear or set the carry/borrow ï¬ag.
0 No carry out of bit 7
1 Carry out of bit 7
7.3 Addressing Modes
Addressing modes deï¬ne the way the CPU accesses operands and data. In the HCS08, all memory, status
and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit
binary address can uniquely identify any memory location. This arrangement means that the same
instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile
program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
90
Freescale Semiconductor
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