MC9S08RC8 Datasheet, PDF (79/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
R
W
Reset
7
PTADD7
0
6
PTADD6
5
PTADD5
4
PTADD4
3
PTADD3
2
PTADD2
0
0
0
0
0
Figure 6-8. Data Direction for Port A (PTADD)
1
PTADD1
0
0
PTADD0
0
Table 6-3. PTADD Field Descriptions
Field
Description
7:0
PTADD[7:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.6.2 Port B Registers (PTBD, PTBPE, and PTBDD)
Port B pins used as general-purpose I/O pins are controlled by the port B data (PTBD), data direction
(PTBDD), and pullup enable (PTBPE) registers.
R
W
Reset
7
PTBD7
0
6
PTBD6
5
PTBD5
4
PTBD4
3
PTBD3
2
PTBD2
0
0
0
0
0
Figure 6-9. Port B Data Register (PTBD)
1
PTBD1
0
0
PTBD0
0
Table 6-4. PTBD Field Descriptions
Field
Description
7:0
PTBD[7:0]
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
79