MC9S08RC8 Datasheet, PDF (140/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer/PWM (TPM)
Table 10-2. TPM Clock Source Selection
CLKSB:CLKSA
TPM Clock Source to Prescaler Input
0:0
No clock selected (TPM disabled)
0:1
Bus rate clock (BUSCLK)
1:0
Fixed system clock (XCLK)
1:1
External source (TPM1 Ext Clk)¹,²
1. The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency.
2. When the TPM1CH0 pin is selected as the TPM clock source, the corresponding ELS0B:ELS0A control bits should be set to
0:0 so channel 0 does not try to use the same pin for a conflicting function.
Table 10-3. Prescale Divisor Selection
PS2:PS1:PS0
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
TPM Clock Source Divided-By
1
2
4
8
16
32
64
128
10.7.2 Timer Counter Registers (TPM1CNTH:TPM1CNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPM1CNTH or TPM1CNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPM1CNTH or
TPM1CNTL, or any write to the timer status/control register (TPM1SC).
Reset clears the TPM counter registers.
7
6
5
4
3
2
R Bit 15
14
13
12
11
10
1
0
9
Bit 8
W
Any write to TPM1CNTH clears the 16-bit counter.
Reset
0
0
0
0
0
0
0
0
Figure 10-6. Timer Counter Register High (TPM1CNTH)
R
W
Reset
7
Bit 7
0
140
6
5
4
3
2
1
0
6
5
4
3
2
1
Bit 0
Any write to TPM1CNTL clears the 16-bit counter.
0
0
0
0
0
0
0
Figure 10-7. Timer Counter Register Low (TPM1CNTL)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor