MC9S08RC8 Datasheet, PDF (143/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer/PWM (TPM)
CPWMS
X
0
1
MSnB:MSnA
XX
00
01
1X
XX
Table 10-5. Mode, Edge, and Level Selection
ELSnB:ELSnA
00
01
10
11
00
01
10
11
10
X1
10
X1
Mode
Configuration
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
Capture on rising edge only
Input capture Capture on falling edge only
Capture on rising or falling edge
Software compare only
Output compare
Toggle output on compare
Clear output on compare
Set output on compare
Edge-aligned
PWM
High-true pulses (clear output on compare)
Low-true pulses (set output on compare)
Center-aligned
PWM
High-true pulses (clear output on compare-up)
Low-true pulses (set output on compare-up)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
10.7.5 Timer Channel Value Registers (TPM1CnVH:TPM1CnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
7
6
5
4
3
2
R
Bit 15
14
13
12
11
10
W
1
0
9
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 10-11. Timer Channel Value Register High (TPM1CnVH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 10-12. Timer Channel Value Register Low (TPM1CnVL)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
143