MC9S08RC8 Datasheet, PDF (71/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

5.8.7
Resets, Interrupts, and System Configuration
System Power Management Status and Control 1 Register
(SPMSC1)
7
6
5
4
3
2
1
0
R LVDF
0
0
0
0
LVDIE
SAFE
LVDRE⁽¹⁾
W
LVDACK
POR:
0
0
0
0
1
0
0
0
Any other
0
0
0
0
u
0
0
0
reset:
= Unimplemented or Reserved
u = Unaffected by reset
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
1. This bit can be written only one time after reset. Additional writes are ignored.
Table 5-10. SPMSC1 Field Descriptions
Field
Description
7
LVDF
6
LVDACK
5
LVDIE
4
SAFE
3
LVDRE
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect error.
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return logic 0.
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
SAFE System from interrupts — This read/write bit enables hardware to block interrupts and resets from
waking the MCU from stop mode while the supply voltage V_DD is below the V_REARM voltage. For a more detailed
description see Section 5.6.3, “LVD Interrupt and Safe State Operation”
0 Enable pending interrupts and resets
1 Interrupts and resets are blocked while supply voltage is below re-arm voltage
Low-Voltage Detect Reset Enable — This bit enables the LVD reset function. This bit can be written only once
after a reset and additional writes have no meaning or effect. It is set following a POR and is unaffected by any
other resets, including an LVD reset.
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
71