MC9S08RC8 Datasheet, PDF (213/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

Electrical Characteristics
2. When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f_Bus and then samples the level on
the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4. Timing is shown with respect to 20% V_DD and 80% V_DD levels. Temperature range –40°C to 85°C.
RESET PIN
t_extrst
Figure A-6. Reset Timing
BKGD/MS
RESET
t_MSH
t_MSSU
Figure A-7. Active Background Debug Mode Latch Timing
t_ILIH
IRQ
Figure A-8. IRQ Timing
A.9.2 Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
213