MC9S08RC8 Datasheet, PDF (168/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
13.3.1 SPI Clock Formats
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI
system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock
formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses
between two different clock phase relationships between the clock and data.
Figure 13-5 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shown
for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the
sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the
setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies
for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI
input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from
a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies
to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes
to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the
eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.
BIT TIME #
(REFERENCE)
1
2
...
6
7
8
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
BIT 7
BIT 6
BIT 0
BIT 1
...
BIT 2
BIT 1
BIT 0
...
BIT 5
BIT 6
BIT 7
Figure 13-5. SPI Clock Formats (CPHA = 1)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
168
Freescale Semiconductor