MC9S08RC8 Datasheet, PDF (113/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

16 BITS
0
CMTCMD1:CMTCMD2
17-BIT DOWN COUNTER *
16
LOAD _.
=?
16
SPACE PERIOD REGISTER *
Carrier Modulator Transmitter (CMT) Block Description
MODE
CLOCK CONTROL
÷8
CMTCLOCK
. CARRIER OUT (f_CG)
MODULATOR GATE
MODULATOR
OUT
SYSTEM CONTROL
EOC FLAG SET
MODULE INTERRUPT REQUEST
PRIMARY/SECONDARY SELECT
CMTCMD3:CMTCMD4
16 BITS
* DENOTES HIDDEN REGISTER
Figure 8-4. Modulator Block Diagram
8.5.2.1 Time Mode
When the modulator operates in time mode (MCGEN bit is set, BASE bit is clear, and FSK bit is clear),
the modulation mark period consists of an integer number of CMTCLK ÷ 8 clock periods. The modulation
space period consists of zero or an integer number of CMTCLK ÷ 8 clock periods. With an 8 MHz bus and
CMTDIV1:CMTDIV0 = 00, the modulator resolution is 1 µs and has a maximum mark and space period
of about 65.535 ms each. See Figure 8-5 for an example of the time mode and baseband mode outputs.
The mark and space time equations for time and baseband mode are:
t_mark = (CMTCMD1:CMTCMD2 + 1) ÷ (f_CMTCLK ÷ 8)
Eqn. 8-5
t_space = CMTCMD3:CMTCMD4 ÷ (f_CMTCLK ÷ 8)
Eqn. 8-6
where CMTCMD1:CMTCMD2 and CMTCMD3:CMTCMD4 are the decimal values of the concatenated
registers.
NOTE
If the modulator is disabled while the t_mark time is less than the programmed
carrier high time (t_mark < CMTCGH1/f_CMTCLK), the modulator can enter
into an illegal state and end the curent cycle before the programmed value.
Make sure to program t_mark greater than the carrier high time to avoid this
illegal state.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
113