MC9S08RC8 Datasheet, PDF (46/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory
program time provided that the conditions above are met. In the case where the next sequential address is
the beginning of a new row, the program time for that byte will be the standard time instead of the burst
time. This is because the high voltage to the array must be disabled and then enabled again. If a new burst
command has not been queued before the current command completes, then the charge pump will be
disabled and high voltage removed from the array.
START
0
FACCERR ?
1
CLEAR ERROR
WRITE TO FCDIV⁽¹⁾
FCBEF ?
0
1
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
(1) _{Required only once}
after reset.
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF ⁽²⁾
(2) _{Wait at least four cycles before}
checking FCBEF or FCCF.
FPVIO OR
YES
FACCERR ?
YES
NO
NEW BURST COMMAND ?
NO
ERROR EXIT
0
FCCF ?
1
DONE
Figure 4-4. FLASH Burst Program Flowchart
4.4.5 Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed:
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
46
Freescale Semiconductor