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MC9S08RC8 Datasheet, PDF (156/234 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Serial Communications Interface (S08SCIV1)
Table 12-7. SCI1C3 Register Field Descriptions (continued)
Field
3
ORIE
2
NEIE
1
FEIE
0
PEIE
Description
Overrun Interrupt Enable â This bit enables the overrun ï¬ag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
Noise Error Interrupt Enable â This bit enables the noise ï¬ag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
Framing Error Interrupt Enable â This bit enables the framing error ï¬ag (FE) to generate hardware interrupt
requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
Parity Error Interrupt Enable â This bit enables the parity error ï¬ag (PF) to generate hardware interrupt
requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
12.2.7 SCI Data Register (SCI1D)
This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic ï¬ag clearing mechanisms for the SCI status ï¬ags.
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
Reset
0
0
0
0
0
0
0
0
Figure 12-10. SCI Data Register (SCI1D)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
156
Freescale Semiconductor
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