MC9S08RC8 Datasheet, PDF (120/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

Carrier Modulator Transmitter (CMT) Block Description
7
6
5
4
3
2
1
0
R
SL7
SL6
SL5
SL4
SL3
SL2
SL1
SL0
W
Reset
u
u
u
u
u
u
u
u
u = Unaffected
Figure 8-11. Carrier Generator Data Register Low 2 (CMTCGL2)
Table 8-6. CMTCGL2 Field Descriptions
Field
7:0
SL[7:0]
Description
Secondary Carrier Low Time Data Values — When selected, these bits contain the number of input clocks
required to generate the carrier high and low time periods. When operating in time mode (see Section 8.5.2.1,
“Time Mode"), this register pair is never selected. When operating in FSK mode (see Section 8.5.2.3, “FSK
Mode"), this register pair and the primary register pair are alternatively selected under control of the modulator.
The secondary carrier high and low time values are unaffected out of reset. These bits must be written to nonzero
values before the carrier generator is enabled when operating in FSK mode.
8.6.2 CMT Output Control Register (CMTOC)
This register is used to control the IRO output of the CMT module.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
IROL
CMTPOL IROPEN
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-12. CMT Output Control Register (CMTOC)
Table 8-7. CMTOC Field Descriptions
Field
Description
7
IROL
6
CMTPOL
5
IROPEN
IRO Latch Control — Reading IROL reads the state of the IRO latch. Writing IROL changes the state of the IRO
pin when the MCGEN bit is clear in the CMTMSC register and the IROPEN bit is set.
CMT Output Polarity — The CMTPOL bit controls the polarity of the IRO pin output of the CMT.
0 IRO pin is active low
1 IRO pin is active high
IRO Pin Enable — The IROPEN bit is used to enable and disable the IRO pin. When the pin is enabled, it is an
output that drives out either the CMT transmitter output or the state of the IROL bit depending on whether the
MCGEN bit in the CMTMSC register is set. Also, the state of the output is either inverted or not depending on
the state of the CMTPOL bit. When the pin is disabled, it is in a high impedance state so it doesn’t draw any
current. The pin is disabled during reset.
0 IRO pin disabled
1 IRO pin enabled as output
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
120
Freescale Semiconductor