MC9S08RC8 Datasheet, PDF (111/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

CMTCLK
BASE
FSK
MCGEN
CMTCGH2
CMTCGH1
=?
Carrier Modulator Transmitter (CMT) Block Description
CLK _{8-BIT UP COUNTER}
CLR
PRIMARY/
SECONDARY
SELECT
CARRIER OUT (f_CG)
=?
CMTCGL1
CMTCGL2
Figure 8-3. Carrier Generator Block Diagram
The high/low time counter is an 8-bit up counter. After each increment, the contents of the counter are
compared with the appropriate high or low count value register. When the compare value is reached, the
counter is reset to a value of $01, and the compare is redirected to the other count value register.
Assuming that the high time count compare register is currently active, a valid compare will cause the
carrier output to be driven low. The counter will continue to increment (starting at reset value of $01).
When the value stored in the selected low count value register is reached, the counter will again be reset
and the carrier output will be driven high.
The cycle repeats, automatically generating a periodic signal that is directed to the modulator. The lowest
frequency (maximum period) and highest frequency (minimum period) that can be generated are defined
as:
f_max = f_CMTCLK ÷ (2 x 1) Hz
f_min = f_CMTCLK ÷ (2 x (2⁸ – 1)) Hz
In the general case, the carrier generator output frequency is:
Eqn. 8-1
Eqn. 8-2
Where:
f_CG = f_CMTCLK ÷ (Highcount + Lowcount) Hz
0 < Highcount < 256 and
0 < Lowcount < 256
Eqn. 8-3
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
111