MC9S08RC8 Datasheet, PDF (63/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

Resets, Interrupts, and System Configuration
5.6.1 Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the V_POR level, the
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in
reset until the supply has risen above the V_LVD level. Both the POR bit and the LVD bit in SRS are set
following a POR.
5.6.2 LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition. This is done by
setting LVDRE to 1. LVDRE is a write-once bit that is set following a POR and is unaffected by other
resets. When LVDRE = 1, setting the SAFE bit has no effect. After an LVD reset has occurred, the LVD
system will hold the MCU in reset until the supply voltage is above the V_LVD level. The LVD bit in the
SRS register is set following either an LVD reset or POR.
5.6.3 LVD Interrupt and Safe State Operation
When the voltage on the supply pin V_DD drops below V_LVD and the LVD circuit is configured for interrupt
operation (LVDIE is set and LVDRE is clear), an LVD interrupt will occur. The LVD trip point is set above
the minimum voltage at which the MCU can reliably operate, but the supply voltage may still be dropping.
It is recommended that the user place the MCU in the safe state as soon as possible following a LVD
interrupt. For systems where the supply voltage may drop so rapidly that the MCU may not have time to
service the LVD interrupt and enter the safe state, it is recommended that the LVD be configured to
generate a reset. The safe state is entered by executing a STOP instruction with the SAFE bit in the system
power management status and control 1 (SPMSC1) register set while in a low voltage condition
(LVDF = 1).
After the LVD interrupt has occurred, the user may configure the system to block all interrupts, resets, or
wakeups by writing a 1 to the SAFE bit. While SAFE =1 and V_DD is below V_REARM all interrupts, resets,
and wakeups are blocked. After V_DD is above V_REARM, the SAFE bit is ignored (the SAFE bit will still
read a 1). After setting the SAFE bit, the MCU must be put into either the stop3 or stop2 mode before the
supply voltage drops below the minimum operating voltage of the MCU. The supply voltage may now
drop to a level just above the POR trip point and then restored to a level above V_REARM and the MCU state
(in the case of stop3) and RAM contents will be preserved. When the supply voltage has been restored,
interrupts, resets, and wakeups are then unblocked. When the MCU has recovered from stop mode, the
SAFE bit should be cleared.
5.6.4 Low-Voltage Warning (LVW)
The LVD system has a low-voltage warning flag to indicate to the user that the supply voltage is
approaching, but is still above, the low-voltage detect voltage. The LVW does not have an interrupt
associated with it. However, the FLASH memory cannot be reliably programmed or erased below the
V_LVW level, so the status of the LVWF bit in the system power management status and control 2 (SPMSC2)
register must be checked before initiating any FLASH program or erase operation.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
63