MC9S08RC8 Datasheet, PDF (33/234 Pages) Freescale Semiconductor, Inc – Microcontrollers

Modes of Operation
3.6.4 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the Development Support chapter of this data sheet. If ENBDM is set when
the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when
the MCU enters stop mode so background debug communication is still possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation. The MCU
cannot enter either stop1 mode or stop2 mode if ENBDM is set.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After active background mode is entered, all background
commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the active
background mode is enabled.
Table 3-2. BDM Enabled Stop Mode Behavior
Mode
Stop3
PDC
Don’t
care
PPDC
Don’t
care
CPU, Digital
Peripherals,
FLASH
Standby
RAM
Standby
OSC
On
ACMP Regulator I/O Pins
RTI
Standby
On
States
held
Optionally on
3.6.5 LVD Reset Enabled
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD reset is enabled in stop by setting the LVDRE bit in SPMSC1 when the CPU
executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user
attempts to enter either stop1 or stop2 with the LVD reset enabled (LVDRE = 1) the MCU will instead
enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when LVD reset is enabled.
Table 3-3. LVD Enabled Stop Mode Behavior
Mode
Stop3
PDC
Don’t
care
PPDC
Don’t
care
CPU, Digital
Peripherals,
FLASH
Standby
RAM
Standby
OSC
On
ACMP Regulator I/O Pins
RTI
Standby
On
States
held
Optionally on
3.6.6 On-Chip Peripheral Modules in Stop Mode
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks are kept alive to the background debug logic, clocks to
the peripheral systems are halted to reduce power consumption.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
33