XRT72L54 Datasheet, PDF (9/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
ADVANCED CONFIDENTIAL
REV. P1.1.2
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 185
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 185
4.2.4 The Transmit DS3 Framer Block ........................................................................................................... 185
Figure 64. A Simple Illustration of the Transmit DS3 Framer Block and the associated paths to other Func-
tional Blocks ........................................................................................................................................ 186
TX DS3 CONFIGURATION REGISTER (ADDRESS = 0X30) ........................................................................ 187
TABLE 28: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 7 (TX YELLOW ALARM) WITHIN THE TX DS3 CON-
FIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION .......................... 187
TABLE 29: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 6 (TX X-BITS) WITHIN THE TX DS3 CONFIGURA-
TION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ..................................... 187
TABLE 30: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 5 (TX IDLE) WITHIN THE TX DS3 CONFIGURATION
REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER ACTION .......................................................... 188
TABLE 31: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 4 (TX AIS PATTERN) WITHIN THE TX DS3 CON-
FIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION .......................... 188
TABLE 32: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (TX LOS) WITHIN THE TX DS3 CONFIGURATION
REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ............................................. 189
TX DS3 M-BIT MASK REGISTER, ADDRESS = 0X35 ............................................................................... 189
TX DS3 F-BIT MASK1 REGISTER, ADDRESS = 0X36 .............................................................................. 190
TX DS3 F-BIT MASK2 REGISTER, ADDRESS = 0X37 .............................................................................. 190
TX DS3 F-BIT MASK3 REGISTER, ADDRESS = 0X38 .............................................................................. 190
TX DS3 F-BIT MASK4 REGISTER, ADDRESS = 0X39 .............................................................................. 190
4.2.5 The Transmit DS3 Line Interface Block ................................................................................................. 190
Figure 65. Approach to Interfacing the XRT72L54 Framer IC to the XRT73L04 DS3/E3/STS-1 Transmitter
LIU (one channel shown) .................................................................................................................... 191
Figure 66. A Simple Illustration of the Transmit DS3 LIU Interface block .......................................... 192
Figure 67. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit DS3
LIU Interface is operating in the Unipolar Mode .................................................................................. 192
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 193
TABLE 33: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O CON-
TROL REGISTER AND THE TRANSMIT DS3 FRAMER LINE INTERFACE OUTPUT MODE ................................ 193
Figure 68. Illustration of AMI Line Code ............................................................................................. 194
Figure 69. Illustration of two examples of B3ZS Encoding ................................................................. 194
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 195
TABLE 34: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE I/O CONTROL REGISTER AND THE BI-
POLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT DS3 LIU INTERFACE BLOCK ................................. 195
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 195
TABLE 35: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................... 195
Figure 70. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG
are configured to be updated on the rising edge of TxLineClk ............................................................ 196
Figure 71. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG
are configured to be updated on the falling edge of TxLineClk ........................................................... 196
4.2.6 Transmit Section Interrupt Processing .................................................................................................. 196
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 197
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) .................................. 197
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) .................................. 198
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ................................................... 198
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ................................................... 199
4.3 THE RECEIVE SECTION OF THE XRT72L54 (DS3 MODE OPERATION) ................................................................. 199
Figure 72. A Simple Illustration of the Receive Section of the XRT72L54, when it has been configured to
operate in the DS3 Mode .................................................................................................................... 199
4.3.1 The Receive DS3 LIU Interface Block ................................................................................................... 199
Figure 73. A Simple Illustration of the Receive DS3 LIU Interface Block ........................................... 200
Figure 74. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data
200
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