XRT72L54 Datasheet, PDF (11/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
ADVANCED CONFIDENTIAL
REV. P1.1.2
RX DS3 LAPD STATUS REGISTER (ADDRESS = 0X19) .......................................................................... 219
TABLE 41: THE RELATIONSHIP BETWEEN RXLAPDTYPE[1:0] AND THE RESULTING LAPD MESSAGE TYPE AND
SIZE ...................................................................................................................................................... 220
Figure 86. Flow Chart depicting the Functionality of the LAPD Receiver .......................................... 221
4.3.4 The Receive Overhead Data Output Interface ...................................................................................... 221
Figure 87. A Simple Illustration of the Receive Overhead Output Interface block ............................. 222
TABLE 42: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK ................................................................................................................................ 223
Figure 88. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 1). ............................................................................................................ 223
TABLE 43: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXO-
HFRAME WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT
PIN ....................................................................................................................................................... 224
Figure 89. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method
1). ........................................................................................................................................................ 226
TABLE 44: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (METHOD 2) ............................................................................................................. 227
Figure 90. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 2). ............................................................................................................ 228
TABLE 45: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES ((SINCE RXOHFRAME
WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN
229
Figure 91. Illustration of the signals that are output via the Receive Overhead Data Output Interface block
(for Method 2). ..................................................................................................................................... 231
4.3.5 The Receive Payload Data Output Interface ......................................................................................... 231
Figure 92. A Simple illustration of the Receive Payload Data Output Interface block ........................ 232
TABLE 46: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT IN-
TERFACE BLOCK .................................................................................................................................... 233
Figure 93. Illustration of the XRT72L54 DS3/E3 Framer IC being interfaced to the Receive Terminal Equip-
ment (Serial Mode Operation) ............................................................................................................. 234
Figure 94. An Illustration of the behavior of the signals between the Receive Payload Data Output Interface
block of the XRT72L54 and the Terminal Equipment (Serial Mode Operation) .................................. 235
Figure 95. Illustration of the XRT72L54 DS3/E3 Framer IC being interfaced to the Receive Section of the
Terminal Equipment (Nibble-Mode Operation) ................................................................................... 236
Figure 96. An Illustration of the Behavior of the signals between the Receive Payload Data Output Interface
Block of the XRT72L54 and the Terminal Equipment (Nibble-Mode Operation). ............................... 237
4.3.6 Receive Section Interrupt Processing ................................................................................................... 237
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 238
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 238
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 239
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 239
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 240
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 240
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 240
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 241
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 241
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 242
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 242
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 243
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 243
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 243
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 244
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ...................................................................................... 244
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 244
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 245
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