XRT72L54 Datasheet, PDF (10/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 201
TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................... 201
Figure 75. Illustration on how the Receive DS3 Framer (within the XRT72L54 Framer IC) being interface to
theXRT73L04 LIU, while the Framer is operating in Bipolar Mode (one channel shown) ................... 201
Figure 76. Illustration of AMI Line Code ............................................................................................. 202
Figure 77. Illustration of two examples of B3ZS Decoding ................................................................. 203
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 203
TABLE 37: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REG-
ISTER, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL ................................................................... 203
Figure 78. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the rising edge of RxLineClk ................................................................ 204
Figure 79. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the falling edge of RxLineClk ............................................................... 204
4.3.2 The Receive DS3 Framer Block ............................................................................................................ 204
Figure 80. A Simple Illustration of the Receive DS3 Framer Block and the Associated Paths to the Other
Functional Blocks ................................................................................................................................ 205
Figure 81. The State Machine Diagram for the Receive DS3 Framer block's Frame Acquisition/Mainte-
nance Algorithm ................................................................................................................................... 206
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 207
TABLE 38: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (FRAMING ON PARITY) WITHIN THE RX DS3
CONFIGURATION AND STATUS REGISTER, AND THE RESULTING FRAMING ACQUISITION CRITERIA .............. 207
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 207
TABLE 39: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (F-SYNC ALGO) WITHIN THE RX DS3 CONFIG-
URATION AND STATUS REGISTER, AND THE RESULTING F-BIT OOF DECLARATION CRITERIA USED BY THE RECEIVE
DS3 FRAMER BLOCK ............................................................................................................................. 208
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 208
TABLE 40: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 0 (M-SYNC ALGO) WITHIN THE RX DS3 CONFIG-
URATION AND STATUS REGISTER, AND THE RESULTING M-BIT OOF DECLARATION CRITERIA USED BY THE RE-
CEIVE DS3 FRAMER BLOCK .................................................................................................................... 208
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 208
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 209
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52) ................................. 209
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53) .................................. 209
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 210
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 210
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 211
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 211
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 211
RX DS3 STATUS REGISTER (ADDRESS = 0X11) ..................................................................................... 212
RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 212
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ...................................................................................... 213
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ..................................................................... 213
PMON PARITY ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X54) .......................................... 213
PMON PARITY ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X55) ........................................... 213
Figure 82. A Simple Illustration of the Locations of the Source, Mid-Network and Sink Terminal Equipment
(for CP-Bit Processing) ........................................................................................................................ 214
Figure 83. Illustration of the Presumed Configuration of the Mid-Network Terminal Equipment ........ 215
4.3.3 The Receive HDLC Controller Block ..................................................................................................... 216
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................ 217
RX DS3 FEAC REGISTER (ADDRESS = 0X16) ....................................................................................... 217
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................ 217
Figure 84. Flow Diagram depicting how the Receive FEAC Processor Functions ............................. 218
Figure 85. LAPD Message Frame Format .......................................................................................... 219
RX DS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................ 219
VIII