XRT72L54 Datasheet, PDF (14/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
TABLE 58: THE RELATIONSHIP BETWEEN BIT 4 (AMI/HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE BI-
POLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT E3 LIU INTERFACE BLOCK .................................... 296
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 296
TABLE 59: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................... 296
Figure 125. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG
are configured to be updated on the rising edge of TxLineClk ............................................................ 297
Figure 126. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG
are configured to be updated on the falling edge of TxLineClk ........................................................... 297
5.2.6 Transmit Section Interrupt Processing .................................................................................................. 297
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ...................................................................... 298
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 298
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 299
5.3 THE RECEIVE SECTION OF THE XRT72L54 (E3 MODE OPERATION) .................................................................... 299
Figure 127. A Simple Illustration of the Receive Section of the XRT72L54 configured to operate in the E3
Mode .................................................................................................................................................... 299
5.3.1 The Receive E3 LIU Interface Block ...................................................................................................... 299
Figure 128. A Simple Illustration of the Receive E3 LIU Interface Block ............................................ 300
Figure 129. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data
301
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 301
TABLE 60: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................... 301
Figure 130. Illustration on how a Channel of the Receive E3 Framer (within the XRT72L54 Framer IC) being
interface to theXRT73L04 Line Interface Unit, while operating in Bipolar Mode ................................. 302
Figure 131. Illustration of AMI Line Code ........................................................................................... 303
Figure 132. Illustration of two examples of HDB3 Decoding .............................................................. 303
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 304
TABLE 61: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REG-
ISTER, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL ................................................................... 304
Figure 133. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the rising edge of RxLineClk ................................................................ 305
Figure 134. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the falling edge of RxLineClk ............................................................... 305
5.3.2 The Receive E3 Framer Block ............................................................................................................... 305
Figure 135. A Simple Illustration of the Receive E3 Framer Block and the Associated Paths to the Other
Functional Blocks ................................................................................................................................ 306
Figure 136. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Al-
gorithm ................................................................................................................................................. 307
Figure 137. Illustration of the E3, ITU-T G.751 Framing Format ........................................................ 307
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 308
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 309
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 309
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 309
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 310
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) ................................... 310
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) .................................... 310
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 311
TABLE 62: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK ............................................................................ 311
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 312
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 312
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 312
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 313
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 313
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