XRT72L54 Datasheet, PDF (13/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
ADVANCED CONFIDENTIAL
REV. P1.1.2
TABLE 48: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN
THE XRT72L54 IC ................................................................................................................................ 270
TABLE 49: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ..................... 271
Figure 113. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data Input
Interface (Method 1) ............................................................................................................................ 272
TABLE 50: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK, (SINCE TXO-
HFRAME WAS LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED ................. 273
Figure 114. Illustration of the signal that must occur between the Terminal Equipment and the XRT72L54
in order to configure the XRT72L54 to transmit a Yellow Alarm to the remote terminal equipment ... 274
TABLE 51: DESCRIPTION OF METHOD 2 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ..................... 275
Figure 115. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data Input
Interface (Method 2) ............................................................................................................................ 276
TABLE 52: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES (SINCE THE LAST OCCURRENCE
OF THE TXOHFRAME PULSE) TO THE E3 OVERHEAD BIT, THAT IS BEING PROCESSED BY THE XRT72L54 277
Figure 116. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L54 and the
Terminal Equipment (for Method 2) .................................................................................................... 278
5.2.3 The Transmit E3 HDLC Controller ........................................................................................................ 278
Figure 117. LAPD Message Frame Format ....................................................................................... 279
TABLE 53: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE, WITHIN THE INFOR-
MATION PAYLOAD .................................................................................................................................. 279
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 280
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ..................................................... 280
TABLE 54: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE .................. 281
TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ................................................................. 281
TRANSMIT E3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ..................................................... 281
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 282
TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 282
Figure 118. Flow Chart Depicting how to use the LAPD Transmitter ................................................. 284
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 285
5.2.4 The Transmit E3 Framer Block ............................................................................................................. 286
Figure 119. A Simple Illustration of the Transmit E3 Framer Block and the associated paths to other Func-
tional Blocks ........................................................................................................................................ 287
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 287
TABLE 55: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TX AIS ENABLE) WITHIN THE TX E3 CONFIG-
URATION REGISTER, AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION ................................. 288
TABLE 56: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (TX LOS) WITHIN THE TX E3 CONFIGURATION
REGISTER, AND THE RESULTING TRANSMIT E3 FRAMER BLOCK'S ACTION ............................................... 288
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 288
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35) ................................................................................ 289
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 289
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 290
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48) ................................................................... 290
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49) ................................................................... 290
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A) ...................................................................... 291
5.2.5 The Transmit E3 Line Interface Block ................................................................................................... 291
Figure 120. Approach to Interfacing the XRT72L54 Framer IC to the XRT73L04 DS3/E3/STS-1 LIU 292
Figure 121. A Simple Illustration of the Transmit E3 LIU Interface block ........................................... 293
Figure 122. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit DS3
LIU Interface is operating in the Unipolar Mode .................................................................................. 293
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 294
TABLE 57: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O CON-
TROL REGISTER AND THE TRANSMIT E3 FRAMER LINE INTERFACE OUTPUT MODE .................................. 294
Figure 123. Illustration of AMI Line Code ........................................................................................... 295
Figure 124. Illustration of two examples of HDB3 Encoding .............................................................. 295
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 296
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