XRT72L54 Datasheet, PDF (210/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L54 FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
The XRT72L54 Framer IC is a digital device that
takes DS3 payload and overhead bit information from
some terminal equipment, processes this data and ul-
timately, multiplexes this information into a series of
outbound DS3 frames. However, for DS3 coaxial ca-
ble applications, the XRT72L54 Framer IC lacks the
current drive capability to be able to directly transmit
this DS3 data stream through some transformer-cou-
pled coax cable with enough signal strength for it to
comply with the Isolated Pulse Template require-
ments and be received by the remote receiver.
Therefore, in order to get around this problem, the
Framer IC requires the use of an LIU (Line Interface
Unit) IC. An LIU is a device that has sufficient drive
capability, along with the necessary pulse-shaping
circuitry to be able to transmit a signal through the
transmission medium in a manner that it can (1) com-
ply with the DSX-3 Isolated Pulse Template require-
ments and (2) be reliably received by the Remote Ter-
minal Equipment. Figure 65 presents a circuit draw-
ing depicting the Framer IC interfacing to an LIU
(XRT7300 DS3/E3/STS-1 Transmit LIU).
FIGURE 65. APPROACH TO INTERFACING THE XRT72L54 FRAMER IC TO THE XRT73L04 DS3/E3/STS-1 TRANS-
MITTER LIU (ONE CHANNEL SHOWN)
RxAIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
Rx_LOS_Ch_0
RxFRAME_0
RxSERIAL_CLK_0
RxDATA_IN_0
D[7:0]
A[10:0]
READY_OUT*
ALE
RD*
WR*
XRT72L54_CS*
XRT72L54_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT_0
RxAVDD_0
DVDD_0
U1
C5
B5
A3
C4
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
F20
D20
F19
RxFrame_0
RxClk_0
T20
RxSer_0
MOTO
RxPOS_0 ^F2
RxNEG_0 ^F3
J19
J20
D7
K17
K18
K19
K20
L20
L18
D6
D5
D4
D3
D2
D1
D0
M20
M19
M18
A10
A9
M17
N20
N19
N18
P20
A8
A7
A6
A5
A4
P19
P18
R20
A3
A2
A1
A0
J17
R19
V20
Rdy_Dtck
ALE_AS
P17 ^RDB_DS
R18
H20
WRB_RW
CSB
INT
T19 _RESETB
RxLineClk_0 ^F1
RLOL_0
ExtLOS_0
B8
D9
LLOOP_0
C7
A5
REQB_0
TAOS_0
DMO_0
TxLEV_0
C6
C9
C3
B7
RLOOP_0
ENCODIS_0 (TxOFF_0)
B2
TxPOS_0 ^C1
TxNEG_0 ^D1
TxLineClk_0 ^E2
T18 _NIBBLEINTF
E20
G4
E18
TxFrame_0
TxInClk_0
TxSER_0
XRT72L54_Ch_0
C2
0.01uF
C3
0.01uF
R7
4.7k
78 _RxAVDD0
58
RxDVDD0
75
52
LOSTHR_0
HOST/HW
61 _RPOS0
60 _RNEG0/LCV0
59 _RCLK0
U2
TxAVDD0 ⁴⁷
33
TxAVDD0
RTIP0 ⁸⁰
RRING0 ⁷⁹
XRT71D04_CS* (Optional)
65
64
RLOL_0
RLOS_0
69
70
CS
71
72
110
SCLK
SDI
SDO
REG_RESET*
131 _TxOFF
41 _{TPDATA_0}
40 _{TNDATA_0}
42
66
TCLK_0
EXCLK_0
TTIP0 ³⁴
TRING0 ³²
MTIP0 ³⁵
54
RxDGND0
73 _RxAGND0
MRING0 ³⁶
31
TxAGND0
TxAGND0 ⁴⁹
XRT73L04IV_Ch_0
C5
0.01uF
TxAVDD_0
C4
0.01uF
R1
R2
37.4
37.4
C1
0.01uF
6 _T2 1
43
T3001
R3
1 _T1 6
31.6
R4
34
T3001
R5
31.6
270
R6
270
J1
BNC
1
J2
BNC
1
The Transmit Section of the XRT72L54 contains a
block which is known as the Transmit DS3 LIU Inter-
face block. The purpose of the Transmit DS3 LIU In-
terface block is to take the outbound DS3 data
stream, from the Transmit DS3 Framer block, and to
do the following:
1. Encode this data into one of the following line
codes
a. Unipolar (e.g., Single-Rail)
b. AMI (Alternate Mark Inversion)
c. B3ZS (Bipolar 3 Zero Substitution)
2. And to transmit this data to the LIU IC.
Figure 66 presents a simple illustration of the Trans-
mit DS3 LIU Interface block.
191