XRT72L54 Datasheet, PDF (156/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L54 FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
TABLE 14: INTERRUPT SERVICE ROUTINE LOCATION (IN CODE MEMORY) FOR THE INT0* AND INT1* INTERRUPT
INPUT PINS
INTERRUPT PIN
BRANCH TO LOCATION (IN SYSTEM MEMORY)
INT0*
0x0003
INT1*
0x0013
Therefore, if the user is using either one of these in-
puts as an interrupt request input, then the user must
ensure that the appropriate interrupt service routine
or unconditional branch instruction (to the interrupt
service routine) is located at one of these address lo-
cations.
If the 8051 Microcontroller IC is required to interface
to external components in the data memory space of
sizes greater than 256 bytes, then both Ports 0 and 2
must be used as the address and data lines. Port 0
will function as a multiplexed address/data bus. Dur-
ing the first half of a memory cycle, Port 0 will operate
as the lower address byte. During the second half of
the memory cycle, Port 0 will operate as the bi-direc-
tional data bus. Port 2 will be used as the upper ad-
dress byte. ALE and the use of a 74HC373 transpar-
ent latch device can be used to de-multiplex the Ad-
dress and Data bus signals.
Figure 37 presents a schematic illustrating how the
XRT72L54 DS3/E3 Framer can be interfaced to the
8051 Microcontroller IC.
FIGURE 37. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT72L54 DS3/E3 FRAMER IC TO THE 8051 MICRO-
CONTROLLER
U3
WR
RD
16
17
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
39
38
37
36
35
34
33
32
HW_RESET*
U4
T19
P17
V20
RESET
WR_RW
RD_DS
L18
L20
K20
K19
K18
K17
J20
J19
D0
D1
D2
D3
D4
D5
D6
D7
INT0
INT1
12
13
5.0V
XRT72L54_INT*
ALE ³⁰
21
A8
A9
A10
A11
A12
A13
A14
A15
22
23
24
25
26
27
28
A8
A9
A10
U5
3
4
7
8
13
14
1D
2D
3D
4D
5D
17
18
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
2
5
6
9
12
15
6Q
7Q
8Q
16
19
11
1
LE
OE
5.0V
20 _VCC
ALE
A8
A9
A10
74HC373
ALE
XRT72L54_INT*
XRT72L54_CS*
R19 _{ALE_AS}
R20
P18
P19
P20
N18
N19
A0
A1
A2
A3
A4
N20
M17
M18
M19
M20
A5
A6
A7
A8
A9
A10
J17 _{Rdy_Dtck}
H20 _INT
R18 _CS
To Address Decoder
8051
T20
MOTO/INTEL
XRT72L54
The circuitry in Figure 37 will function as follows, dur-
ing a Framer-request interrupt. The Framer device
would request an interrupt from the CPU by asserting
its active low INT output pin. This will cause the
INT0* input pin of the CPU to go "Low”. When this
happens the 8051 CPU will finish executing its cur-
rent instruction, and will then branch program control
to the Framer Device interrupt service routine. In the
case of Figure 37, the interrupt service routine will be
located in 0x0003 in code memory. The 8051 CPU
137