XRT72L54 Datasheet, PDF (157/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L54
REV. P1.1.2
does not issue an Interrupt Acknowledge signal back
to the Framer IC. It will just begin processing through
the Framer’s interrupt service routine. One the CPU
has eliminated the cause(s) of the interrupt request,
the Framer’s INT output pin will be negated (e.g., go
"High”) and the CPU will return from the Interrupt Ser-
vice Routine and resume normal operation.
2.9 INTERFACING THE FRAMER IC TO A MOTOROLA-
TYPE MICROPROCESSOR
This section discusses how to interface the
XRT72L54 DS3/E3 Framer IC to the MC68000 Micro-
processor.
Figure 38 presents a schematic on how to interface
the XRT72L54 DS3/E3 Framer IC to the MC68000
Microprocessor, over an 8-bit wide bi-directional data
bus.
FIGURE 38. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT72L54 DS3/E3 FRAMER IC TO THE MC68000
MICROPROCESSOR
U6
RESET
R/W
DTACK
18
9
10
D0
D1
D2
D3
D4
D5
D6
5
4
3
2
1
64
63
62
D7
D8
D9
D10
D11
D12
D13
D14
D15
61
60
59
58
57
56
55
54
25
IPL0
IPL1
IPL2
24
23
VPA ²¹
FC0
FC1
FC2
28
27
26
AS
UDS
LDS
6
7
8
A1
A2
A3
A4
A5
A6
A7
A8
29
30
31
32
33
34
35
36
A9
A10
37
38
39
A11
A12
A13
A14
A15
A16
A17
A18
A19
40
41
42
43
44
45
46
47
48
A20
A21
A22
A23
49
50
51
MC68000
D[15:8]
5V
U10
HPRI/BIN
15
14
9
7
6
1 - 10
- 11
18
-
-
12
13
- 14
- 15
- 16
1 ^{- 17}
2
4
0/Z10
1/Z11
2/Z12
3/Z13
4/Z14
5/Z15
6/Z16
7/Z17
V18
EN
10
11
12
13
1
2
3
4
5
74HC148
U11
BIN/OCT
1
2
3
1
2
4
6
4
5 ^{& EN}
0
1
2
3
4
5
6
7
15
14
13
12
11
10
9
7
74ACT138
U8A ₁
& ³
2
74HCT00
ADDRESS_STROBE*
DATA_STROBE*
ADDRESS_STROBE*
1 3 U 9 B 4
74HC04
U9A
74HC04
XRT72L54_CS*
DATA_STROBE*
3.3V
5V
To Address Decoder
U12
BIN/OCT
1
2
3
1
2
4
6
4
5 ^{& EN}
0
1
2
3
4
5
6
7
15
14
13
12
11
10
9
7
74ACT138
U7
T19
P17
J17
RESET
WR_RW
Rdy_Dtck
L18
L20
K20
K19
K18
K17
J20
D0
D1
D2
D3
D4
D5
J19
D6
D7
V20
R19
RD_DS
ALE_AS
R20
P18 ^A0
P19
P20
N18
A1
A2
A3
N19
N20
M17
M18
M19
M20
A4
A5
A6
A7
A8
A9
A10
H20
INT
R18 _CS
T20 _MOTO/INTEL
XRT72L54
In general, the approach to interfacing these two de-
vices is straightforward. However, the user must be
aware of the fact that the XRT72L54 DS3/E3 Framer
IC does not provide an interrupt vector to the
MC68000 during an Interrupt Acknowledge cycle.
Therefore, the user must configure his/her design to
support auto-vectored interrupts. Auto-vectored in-
terrupt processing is a feature offered by the
MC68000 Family of Microprocessors, where, if the
microprocessor knows (prior to any IACK cycle) the
Interrupt Level of this current interrupt, and that the
interrupting peripheral does not support vectored in-
terrupts, then the Microprocessor will generate its
own Interrupt Vector. The schematic shown in
Figure 38, has been configured to support auto-vec-
tored interrupts.
Functional Description of Circuit illustrated in
Figure 38.
When the XRT72L54 DS3/E3 Framer IC generates
an Interrupt, the INT output will toggle "Low”. This will
force Input 6, of the Interrupt Priority Encoder chip
(U4) to also toggle "Low”. In response to this, the In-
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