XRT72L54 Datasheet, PDF (37/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
PIN DESCRIPTION
PIN #
PIN NAME
G2
RxNEG[1]
G3
TxFrameRef[1]
G4
TxInClk[0]
G17
TxNibFrame[0]/
ValFCS[0]
G18
RxOHInd[0]
G19
RxNib0[0]/
RxHDLCDat0[0]
XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
TYPE
I
I
I
O
O
O
DESCRIPTION
See Description for Pin F3
See Description for Pin E1
Transmit Framer Reference Clock Input:
This input pin functions as the "Timing Reference" for the Transmit Sec-
tion of the XRT72L54 Framer IC; if the device has been configured to
operate in the "Local-Time" Mode. Further, if the XRT72L54 Framer IC
has been configured to operate in the "Local-Time" Mode, the "Transmit
Payload Data Input Interface will sample the data at the TxSer input pin,
upon the rising edge of "TxInClk".
For E3 applications, the user should apply a 34.368MHz clock signal.
For DS3 applications, the user should apply a 44.736MHz clock signal.
The user can configure the XRT72L54 Framer IC to operate in the
"Local-Time" mode by writing "xxxx xx01" or "xxxx xx1x" into the
"Framer Operating Mode" register (Address = 0x00)
Transmit Frame Boundary Indicator - Nibble/Parallel Interface:
This output pin pulses "high" when the last nibble of a given DS3 or E3
frame is expected at the TxNib[3:0] input pins.
The purpose of this output pin is to alert the Terminal Equipment that it
needs to begin transmission of a new DS3 or E3 frame to the
XRT72L54 device.
Valid Frame Check Sequence:
When the HDLC is on, this pin will go high at the end of a valid Frame
Check Sequence.
Receive Overhead Bit Indicator:
The exact functionality of this output pin depends upon whether the
XRT72L54 Framer IC is operating in the “Serial” or “Nibble-Parallel”
Mode.
Serial Mode Operation:
This output pin pulses "high" (for one bit-period) whenever an "over-
head" bit is being output via the "RxSer" output pin, by the "Receive
Payload Data Output Interface" block.
Nibble-Parallel Mode Operation:
This output pin pulses “high” (for one nibble-period) whenever an “over-
head” nibble is being output via the “RxNib[3:0] output pins, by the
“Receive Payload Data Output Interface” block.
NOTE: The purpose of this output pin is to alert the "Receive Terminal
Equipment" that an overhead bit is being output via the "RxSer" output
pin, and that this data should be ignored.
Receive Nibble Output - 0:
The Framer IC will output "Received data (from the Remote Terminal) to
the local Terminal Equipment via this pin along with RxNib1, RxNib2
and RxNib3.
The data at this pin is updated on the rising edge of the RxClk output
signal.
NOTE: This output pin is active only if the Nibble-Parallel Mode has
been selected.
Receive HDLC Data Output - 0:
This pin contains bit 0 RxHDLC data when the HDLC controller is on.
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