XRT72L54 Datasheet, PDF (19/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
ADVANCED CONFIDENTIAL
REV. P1.1.2
RxNEG are to be sampled on the falling edge of RxLineClk .............................................................. 406
6.3.2 The Receive E3 Framer Block .............................................................................................................. 406
Figure 193. A Simple Illustration of the Receive E3 Framer Block and the Associated Paths to the Other
Functional Blocks ................................................................................................................................ 407
Figure 194. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Al-
gorithm ................................................................................................................................................ 408
Figure 195. Illustration of the E3, ITU-T G.832 Framing Format ........................................................ 409
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 410
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 410
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 411
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 411
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 411
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) ................................... 412
PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) .................................... 412
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 412
TABLE 86: THE RELATIONSHIP BETWEEN THE LOGIC STATE OF THE RXOOF AND RXLOF OUTPUT PINS, AND THE
FRAMING STATE OF THE RECEIVE E3 FRAMER BLOCK ............................................................................ 413
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 413
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 413
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 414
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) ................................................................. 414
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 414
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 415
THE MAINTENANCE AND ADAPTATION (MA) BYTE FORMAT ....................................................................... 415
RXE3 CONFIGURATION & STATUS REGISTER 1 - (E3, ITU-T G.832) (ADDRESS = 0X10) ........................ 415
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ................................................................. 416
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 416
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ........................................................ 416
Figure 196. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with a correct EM Byte. ....................................................................................................... 417
Figure 197. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the FEBE bit (within the MA byte-field) set to “0” ......................................................... 417
Figure 198. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with an incorrect EM Byte. .................................................................................................. 418
Figure 199. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the FEBE bit (within the MA byte-field) set to “1” ......................................................... 419
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 419
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ..................................................... 419
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ...................................................... 420
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 420
PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56) ....................................................... 420
PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57) ........................................................ 420
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 421
6.3.3 The Receive HDLC Controller Block ..................................................................................................... 421
Figure 200. LAPD Message Frame Format ....................................................................................... 422
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................... 423
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................... 423
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 423
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 424
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 424
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 425
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 425
TABLE 87: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MES-
SAGE TYPE/SIZE ................................................................................................................................... 425
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................... 426
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