XRT72L54 Datasheet, PDF (15/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
ADVANCED CONFIDENTIAL
REV. P1.1.2
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ...................................................... 313
RXE3 CONFIGURATION & STATUS REGISTER - 1 G.751 (ADDRESS = 0X10) ........................................... 314
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 314
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ...................................................... 314
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ...................................................... 315
Figure 138. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with a correct BIP-4 Value. ................................................................................................. 315
Figure 139. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the “A” bit set to “0” ...................................................................................................... 316
Figure 140. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with an incorrect BIP-4 value. ............................................................................................. 317
Figure 141. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the “A” bit-field set to “1” .............................................................................................. 317
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) ................................................................. 318
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ..................................................... 318
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ...................................................... 318
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 318
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) ................................................................. 319
5.3.3 The Receive HDLC Controller Block ..................................................................................................... 319
Figure 142. LAPD Message Frame Format ....................................................................................... 320
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18 ............................................................................ 320
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 321
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 321
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 322
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 322
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 322
TABLE 63: THE RELATIONSHIP BETWEEN THE CONTENTS OF RXLAPDTYPE[1:0] BIT-FIELDS AND THE PMDL MES-
SAGE TYPE/SIZE ................................................................................................................................... 323
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18 ............................................................................ 323
RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 323
Figure 143. Flow Chart depicting the Functionality of the LAPD Receiver ........................................ 324
5.3.4 The Receive Overhead Data Output Interface ...................................................................................... 324
Figure 144. A Simple Illustration of the Receive Overhead Output Interface block ........................... 325
Figure 145. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 1). ............................................................................................................ 326
TABLE 64: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (FOR METHOD 1) ..................................................................................................... 327
TABLE 65: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXO-
HFRAME WAS LAST SAMPLED "HIGH”) TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT
PIN ....................................................................................................................................................... 327
Figure 146. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method
1). ........................................................................................................................................................ 328
TABLE 66: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK (METHOD 2) ............................................................................................................. 329
Figure 147. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output
Interface block (for Method 2). ............................................................................................................ 330
TABLE 67: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES (SINCE RXOHFRAME
WAS LAST SAMPLED "HIGH") TO THE E3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ..
331
Figure 148. Illustration of the signals that are output via the Receive Overhead Data Output Interface block
(for Method 2). ..................................................................................................................................... 331
5.3.5 The Receive Payload Data Output Interface ......................................................................................... 332
Figure 149. A Simple illustration of the Receive Payload Data Output Interface block ...................... 332
TABLE 68: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT IN-
TERFACE BLOCK .................................................................................................................................... 333
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