XRT72L54 Datasheet, PDF (3/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
ADVANCED CONFIDENTIAL
REV. P1.1.2
TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
FEATURES ................................................................................................................................................. 1
APPLICATIONS ........................................................................................................................................... 1
Figure 1. Block Diagram of the XRT72L54 ............................................................................................ 1
Figure 2. Pin Out ofthe XRT72L54 ......................................................................................................... 2
ORDERING INFORMATION ............................................................................................ 2
ELECTRICAL CHARACTERISTICS .............................................................................. 28
ABSOLUTE MAXIMUMS ............................................................................................................................. 28
DC ELECTRICAL CHARACTERISTICS ......................................................................................................... 28
AC ELECTRICAL CHARACTERISTICS ......................................................................................................... 28
AC ELECTRICAL CHARACTERISTICS (CONT.) ............................................................................................ 30
1.0 Timing Diagrams ................................................................................................................................. 34
Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L54 Device is operating in
both the DS3 and Loop-Timing Modes ................................................................................................. 34
Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L54 Device is operating
in both the DS3 and Local-Timing Modes ............................................................................................. 34
Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L54 Device is
operating in both the DS3/Nibble and Looped-Timing Modes .............................................................. 35
Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L54 Device is
operating in the DS3/Nibble and Local-Timing Modes .......................................................................... 35
Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .......... 36
Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .......... 36
Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the
rising edge of "TxLineClk" ..................................................................................................................... 37
Figure 10. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the
falling edge of "TxLineClk" .................................................................................................................... 37
Figure 11. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the
rising edge of "RxLineClk" ..................................................................................................................... 38
Figure 12. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the
falling edge of "RxLineClk" .................................................................................................................... 38
Figure 13. Receive Payload Data Output Interface Timing .................................................................. 39
Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ......................... 39
Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ................ 40
Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) .......... 40
Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations .............. 41
Figure 18. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations .............. 41
Figure 19. Microprocessor Interface Timing - Intel Type Read Burst Access Operation ..................... 42
Figure 20. Microprocessor Interface Timing - Intel type Write Burst Access Operation ....................... 42
Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ........ 43
Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ......... 43
Figure 23. Microprocessor Interface Timing - Reset Pulse Width ........................................................ 44
2.0 The Microprocessor Interface Block ................................................................................................. 45
2.1 CHANNEL SELECTION WITHIN THE XRT72L54 DEVICE .......................................................................................... 45
TABLE 1: THE RELATIONSHIP BETWEEN ADDRESS BITS A9, A10 AND THE SELECTED CONFIGURATION REGISTER
BANK ...................................................................................................................................................... 45
Figure 24. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC .......... 46
2.2 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL .............................................................................................. 46
TABLE 2: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH
THE INTEL AND MOTOROLA MODES .......................................................................................................... 47
TABLE 3: PIN DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - WHILE THE MICROPROCESSOR INTER-
FACE IS OPERATING IN THE INTEL MODE .................................................................................................. 47
TABLE 4: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE MICROPROCESSOR IN-
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