XRT72L54 Datasheet, PDF (39/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
PIN DESCRIPTION
PIN #
PIN NAME
J4
TxPOS[1]
J9
GND
J10
GND
J11
GND
J12
GND
J17
RDY_DTCK
J18
NC
J19
D[7]
J20
D[6]
K1
RxNEG[3]
K2
TxFrameRef[3]
K3
RxNEG[2]
K4
VDD
K9
GND
K10
GND
K11
GND
K12
GND
K17
D[5]
K18
D[4]
K19
D[3]
K20
D[2]
XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
TYPE
O
****
****
****
****
O
DESCRIPTION
See Description for Pin C1
Ground
Ground
Ground
Ground
READY or DTACK:
This active-low output pin will function as the READY output, when the
microprocessor interface is running in the "Intel" Mode; and will function
as the DTACK output, when the microprocessor interface is running in
the "Motorola" Mode.
"Intel" Mode - READY Output:
When the Framer negates this output pin (e.g., toggles it "low"), it indi-
cates (to the µP) that the current READ or WRITE cycle is to be
extended until this signal is asserted (e.g., toggled "high").
"Motorola" Mode - DTACK (Data Transfer Acknowledge) Output:
The Framer device will assert this pin in order to inform the local micro-
processor that the present READ or WRITE cycle is nearly complete. If
the Framer device requires that the current READ or WRITE cycle be
extended, then the Framer will delay its assertion of this signal. The
68000 family of µPs requires this signal from its peripheral devices, in
order to quickly and properly complete a READ or WRITE cycle.
I/O
MSB of Bi-Directional Data Bus (Microprocessor Interface Sec-
tion):
This pin, along with pins D0 - D6, function as the Microprocessor Inter-
face bi-directional data bus, and is intended to be interfaced to the
"local" microprocessor.
I/O
See Description for Pin J19
I
See Description for Pin F3
I
See Description for Pin E1
I
See Description for Pin F3
****
Power Supply +3.3v ± 5%
****
Ground
****
Ground
****
Ground
****
Ground
I/O
See Description for Pin J19
I/O
See Description for Pin J19
I/O
See Description for Pin J19
I/O
See Description for Pin J19
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