XRT72L54 Datasheet, PDF (25/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
PRELIMINARY
PIN DESCRIPTION
PIN #
PIN NAME
B8
RLOL[0]
B9
DMO[1]
B10
RxOH[1]/
RxHDLCDat6[1]
B11
TxOHIns[1]/
TxHDLCDat4[1]
B12
TxAISEn[1]
B13 RxOHEnable[0]/
RxHDLCDat5[0]
B14 TxOHEnable[0]/
TxHDLCDat7[0]
XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
TYPE
I
I
O
I
I
O
O
I
DESCRIPTION
Receive Loss of Lock Indicator - from the XRT7300 DS3/E3 Line
Interface Unit IC:
This input pin is intended to be connected to the RLOL (Receive Loss of
Lock) output pin of the XRT7300 Line Interface Unit IC. The user can
monitor the state of this pin by reading the state of Bit 1 (RLOL) within
the Line Interface Scan Register (Address = 0x81).
If this input pin is "low", then it means that the "clock recovery phase-
locked-loop" circuitry, within the XRT7300 device is properly locked onto
the incoming DS3 E3 data-stream; and is properly recovering clock and
data from this DS3/E3 data-stream. However, if this input pin is "high",
then it means that the phase-locked-loop circuitry, within the XRT7300
device has lost lock with the incoming DS3 or E3 data-stream, and is
not properly recovering clock and data.
For more information on the operation of the XRT7300 DS3/E3 Line
Interface Unit IC, please consult the "XRT7300 DS3/E3 Line Interface
Unit" data sheet.
If the customer is not using the XRT7300 DS3/E3 Line Interface Unit IC,
he/she can use this input pin for other purposes.
See Description for Pin C9
See Description for Pin C12
See Description for Pin C14
See Description for Pin B15
Receive Overhead Enable Indicator:
The XRT72L54 device will assert this output signal for one “RxOutClk”
period when it is safe for the Terminal Equipment to sample the data on
the “RxOH” output pin.
Receive HDLC Data Output - 5:
This pin contains bit 5 RxHDLC data when the HDLC controller is on.
Transmit Overhead Input Enable:
The XRT72L54 device will assert this signal, for one “TxInClk” period,
just prior to the instant that the “Transmit Overhead Data Input Interface”
will be sampling and processing an overhead bit.
If the Terminal Equipment intends to insert its own value for an over-
head bit, into the outbound DS3 or E3 frame, it is expected to sample
the state of this signal, upon the falling edge of “TxInClk”. Upon sam-
pling the “TxOHEnable” high, the Terminal Equipment should (1) place
the desired value of the overhead bit, onto the “TxOH” input pin and (2)
assert the “TxOHIns” input pin. The Transmit Overhead Data Input Inter-
face” block will sample and latch the data on the “TxOH” signal, upon
the rising edge of the very next “TxInClk” input signal.
Transmit HDLC Data Input - 7:
This pin accepts bit 7 TxHDLC data when the HDLC controller is turned
on.
6