XRT72L54 Datasheet, PDF (220/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L54 FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
II/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
Disable TxLOC
R/W
1
LOC
RO
0
Disable
RxLOC
R/W
1
AMI/ZeroSup*
R/W
0
Table 36 relates the value of this bit-field to the Re-
ceive DS3 LIU Interface Input Mode.
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
TxLine CLK
Invert
R/W
0
BIT 1
RxLine CLK
Invert
R/W
0
BIT 0
Reframe
R/W
0
TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 3
0
1
RECEIVE DS3 LIU INTERFACE INPUT MODE
.Bipolar Mode (Dual Rail): AMI or B3ZS Line Codes are Transmitted and Received.
Unipolar Mode (Single Rail) Mode of transmission and reception of DS3 data is selected.
NOTES:
1. The default condition is the Bipolar Mode.
2. This selection also effects the Transmit DS3 Framer
Line Interface Output Mode
4.3.1.2 Bipolar Decoding
If the Receive DS3 LIU Interface block is operating in
the Bipolar Mode, then it will receive the DS3 data
pulses via both the RxPOS, RxNEG, and the RxLi-
neClk input pins. Figure 75 presents a circuit dia-
gram illustrating how the Receive DS3 LIU Interface
block interfaces to the Line Interface Unit while the
Framer is operating in Bipolar mode. The Receive
DS3 LIU Interface block can be configured to decode
the incoming data from either the AMI or B3ZS line
codes.
FIGURE 75. ILLUSTRATION ON HOW THE RECEIVE DS3 FRAMER (WITHIN THE XRT72L54 FRAMER IC) BEING INTER-
FACE TO THEXRT73L04 LIU, WHILE THE FRAMER IS OPERATING IN BIPOLAR MODE (ONE CHANNEL SHOWN)
RxAVDD_0
TxAVDD_0
DVDD_0
C2
0.01uF
C5
0.01uF
C4
0.01uF
C3
0.01uF
R7
4.7k
RxAIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
Rx_LOS_Ch_0
RxFRAME_0
RxSERIAL_CLK_0
RxDATA_IN_0
D[7:0]
A[10:0]
U1
C5
B5
A3
C4
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
F20
D20
F19
T20
RxFrame_0
RxClk_0
RxSer_0
MOTO
J19
J20
K17
K18
K19
K20
L20
L18
D7
D6
D5
D4
D3
D2
D1
D0
F2
RxPOS_0
RxNEG_0 ^F3
RxLineClk_0 ^F1
RLOL_0
ExtLOS_0
B8
D9
78
RxAVDD0
58
RxDVDD0
75
52
LOSTHR_0
HOST/HW
61
RPOS0
60 _RNEG0/LCV0
59 _RCLK0
U2
47
TxAVDD0
33
TxAVDD0
80
RTIP0
RRING0 ⁷⁹
6 _T2 1
43
T3001
J1
BNC
1
65
64
RLOL_0
RLOS_0
R1
R2
37.4
37.4
M20
M19
M18
M17
N20
A10
A9
A8
A7
LLOOP_0
REQB_0
TAOS_0
C7
A5
C6
C9
69
70
71
72
CS
SCLK
SDI
C1
0.01uF
N19
N18
P20
P19
P18
A6
A5
A4
A3
A2
DMO_0
TxLEV_0
C3
RLOOP_0 ^B7
B2
XRT71D04_CS* (Optional)
110
SDO
REG_RESET*
131
R20
A1
A0
ENCODIS_0 (TxOFF_0)
TxOFF
READY_OUT*
ALE
RD*
WR*
XRT72L54_CS*
XRT72L54_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT_0
J17
R19
Rdy_Dtck
V20
P17
ALE_AS
RDB_DS
R18
H20
WRB_RW
CSB
INT
T19 _RESETB
T18 _NIBBLEINTF
E20
G4
E18
TxFrame_0
TxInClk_0
TxSER_0
C1
TxPOS_0
TxNEG_0 ^D1
TxLineClk_0 ^E2
41
TPDATA_0
34
TTIP0
40 _{TNDATA_0}
42
66
TCLK_0
EXCLK_0
54 _RxDGND0
TRING0 ³²
R5
MTIP0 ³⁵
270
R6
MRING0 ³⁶
270
TxAGND0 ³¹
R3
1 _T1 6
31.6
R4
34
T3001
31.6
J2
BNC
1
73 _RxAGND0
TxAGND0 ⁴⁹
XRT72L54_Ch_0
XRT73L04IV_Ch_0
201