XRT72L54 Datasheet, PDF (64/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L54 FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
2.0 THE MICROPROCESSOR INTERFACE
BLOCK
The Microprocessor Interface section supports com-
munication between the local microprocessor (µP)
and the Framer IC. In particular, the Microprocessor
Interface section supports the following operations
between the local microprocessor and the Framer.
• Channel Selection
• The writing of configuration data into the Framer
on-chip (addressable) registers.
• The writing of an outbound PMDL (Path Mainte-
nance Data Link) message into the Transmit LAPD
Message buffer (within the Framer IC).
• The Framer IC's generation of an Interrupt Request
to the µP.
• The µP's servicing of the interrupt request from the
Framer IC.
• The monitoring of the system's health by periodi-
cally reading the on-chip Performance Monitor reg-
isters.
• The reading of an inbound PMDL Message from
the Receive LAPD Message Buffer (within the
Framer IC).
Each of these operations (between the local micro-
processor and the Framer IC) will be discussed in
some detail, throughout this data sheet.
2.1 CHANNEL SELECTION WITHIN THE XRT72L54
DEVICE
The XRT72L54 4-Channel DS3/E3 Clear Channel
Framer IC consists of four independent banks of
"Configuration" registers. Each of these banks are
identical and correspond to each of the four channels
within the XRT72L54. The XRT72L54 permits the us-
er to select and access any one of these Configura-
tion Register Banks, via the two (2) Most Significant
Address Pins, A9 and A10.
The relationship between the states of A9 and A10,
and the corresponding "Configuration Register" bank,
is tabulated below.
Table 1, The Relationship between Address Bits A9,
A10 and the Selected "Configuration Register" Bank
TABLE 1: THE RELATIONSHIP BETWEEN ADDRESS BITS
A9, A10 AND THE SELECTED CONFIGURATION
REGISTER BANK
A10 A9 CONFIGURATION REGISTER BANK SELECTED
0 0 Channel 0
0 1 Channel 1
1 0 Channel 2
1 1 Channel 3
The remaining Address Bus pins [A8 through A0] are
used to select the individual configuration registers
(within the selected configuration register bank) for
Read/Write access.
Looking at this Another Way
Each of the four (4) Configuration Register Banks,
within the XRT72L54 DS3/E3 Framer IC has an iden-
tical set of configuration registers. However, address
pins A9 and A10 impose the following address loca-
tion offset, for each of the Configuration Register
Bank within the address space of the XRT72L54 de-
vice.
CONFIGURATION REGISTER ADDRESS OFFSET (WITHIN THE
BANK - CHANNEL NUMBER XRT72L54 ADDRESS SPACE)
0
0x000
1
0x200
2
0x400
3
0x600
Figure 24 presents a simple block diagram of the Mi-
croprocessor Interface Section, within the Framer IC.
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