XRT72L54 Datasheet, PDF (36/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
PIN DESCRIPTION
PIN #
F18
PIN NAME
TxNIBClk[0]/
SndFCS[0]
F19
RxSer[0]/
RxIdle[0]
F20
RxFrame[0]
G1
TxInClk[1]
TYPE
O
I
O
O
I
DESCRIPTION
Transmit Nibble Clock Signal:
If the user opts to operate the XRT72L54 device in the “Nibble-
Parallel” mode, then the XRT72L54 device will derive this clock
signal from either the “TxInClk” or the “RxLineClk” signal (de-
pending upon which signal is selected as the timing reference).
The user is advised to configure the Terminal Equipment to out-
put the “outbound” payload data (to the XRT72L54 Framer IC)
onto the “TxNib[3:0]” input pins, upon the rising edge of this
clock signal.
NOTES:
1. For DS3 applications, the XRT72L54 Framer IC will output 1176
clock edges (to the Terminal Equipment) for each “outbound”
DS3 frame.
2. For E3, ITU-T G.832 applications, the XRT72L54 Framer IC will
output 1074 clock edges (to the Terminal Equipment) for each
“outbound” E3 frame.
3. For E3, ITU-T G.751 applications, the XRT72L54 Framer IC will
output 384 clock edges (fo the Terminal Equipment) for each
“outbound” E3 frame.
Send Frame Check Sequence:
When the HDLC controller is turned on, this pin is driven “high” during
the time when FCS bytes are being sent after a valid HDLC message.
Receive Serial Output:
If the user opts to operate the XRT72L54 device in the "serial" mode,
then the chip will output the payload data, of the incoming DS3 or E3
frames, via this pin. The XRT72L54 device will output this data upon the
rising edge of RxClk.
The user is advised to design the Terminal Equipment such that it will
sample this data on the falling edge of RxClk.
NOTE: This signal is only active if the "NibInt" input pin is pulled "low".
Receive Idle:
This pin will go high indicating the idle period of sent HDLC data pack-
ets. Also, in combination with ValFCS it can indicate error conditions.
Receive Boundary of DS3 or E3 Frame Output Indicator:
The exact functionality of this output pin depends upon whether the
XRT72L54 Framer IC is operating in the “Serial” or “Nibble-Parallel”
Mode.
Serial Mode Operation:
The Receive Section of the XRT72L54 device will pulse this output pin
“high” (for one bit-period) when the “Receive Payload Data Output Inter-
face” block is driving the very first bit of a given DS3 or E3 frame, onto
the “RxSer” output pin.
Nibble-Parallel Operation:
The Receive Section of the XRT72L54 device will pulse this output pin
“high” (for one nibble-period), when the “Receive Payload Data Output
Interface” block is driving the very first nibble of a given DS3 or E3
frame, onto the “RxNib[3:0] output pins.
See Description for Pin G4
17