XRT72L54 Datasheet, PDF (33/484 Pages) Exar Corporation – FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
PIN DESCRIPTION
PIN #
PIN NAME
E1
TxFrameRef[0]
E2
TxLineClk[0]
E3
RxOutClk[0]/
RxHDLCDat7[0]
E4
TDO
E17
TxNib1[0]/
TxHDLCDat1[0]
XRT72L54
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
TYPE
I
O
O
O
I
DESCRIPTION
Transmit Framer Reference Input:
This input pin functions as the "Transmit Frame Generation" reference
signal, if the XRT72L54 device has been configured to operate in the
"Local-Time/Frame Slave" Mode. If the XRT72L54 device has been
configured to operate in the "Local-Time/Frame-Slave" Mode, then the
user's terminal equipment is expected to apply a pulse (to this input pin)
once every 106.4 microseconds (for DS3 applications); once every 125
microseconds (for E3, ITU-T G.832 applications) or once every 44.7
microseconds (for E3, ITU-T G.751 applications).
In the "Local-Time/Frame-Slave" Mode, the Transmit Section of the
XRT72L54 Framer IC will initiate its generation of a new "outbound"
DS3 or E3 frame, upon the rising edge of this signal.
NOTE: The user can configure the XRT72L54 Framer IC to operate in
the "Local Time/Frame Slave" Mode by writing "xxxx xx01" into the
"Framer Operating Mode" Register (Address = 0x00).
Transmit Line Interface Clock:
This clock signal is output to the Line Interface Framer, along with the
TxPOS and TxNEG signals. The purpose of this output clock signal is to
provide the LIU with timing information that it can use to generate the
AMI pulses and deliver them over the transmission medium to the Far-
End Receiver. The user can configure the source of this clock to be
either the RxLineClk (from the Receiver portion of the Framer) or the
TxInClk input. The nominal frequency of this clock signal is 34.368
MHz.
Receive Out Clock - Transmit Terminal Interface Clock for Loop-
Timing:
This clock signal functions as the "Terminal Interface" clock source, if
the XRT72L54 Framer IC is operating in the "loop-timing" mode.
In this mode, the Transmitting Terminal Equipment is expected to input
data to the Framer IC, via the “TxSer” input pin, upon the rising edge of
this clock signal. The XRT72L54 device will use the rising edge of this
clock signal to sample the data at the TxSer input.
This clock signal is a buffered version of the RxLineClk signal.
Receive HDLC Data Output - 7:
This pin contains bit 7 RxHDLC data when the HDLC controller is on.
Test Data Out: Boundary Scan test data output.
Transmit Nibble-Parallel Payload Data Input -1:
The Terminal Equipment is expected to input data, that is intended to be
transmitted to the remote terminal, over an E3 or DS3 transport
medium. The Framer IC will take data, applied to this pin, and insert it
into an outbound "E3 or DS3" frame. The XRT72L54 device will sample
the data that is at these input pins, upon the rising edge of the "TxNib-
Clk" signal.
NOTE: This input pin is active only if the Nibble-Parallel Mode has been
selected.
Transmit HDLC Data Input - 1:
This pin accepts bit 1 TxHDLC data when the HDLC controller is turned
on.
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