MC80F0424 Datasheet, PDF (99/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0424/0432/0448
WDT or WT
Interrupt Request
=0
IFWDT
=1
WDT Interrupt
Routine
Clear IFWDT
=0
IFWT
=1
WT Interrupt
Routine
Clear IFWT
RETI
UART0(UART1)
Interrupt Request
=0
IFTX0(IFTX1)
=1
TX0(TX1) Interrupt
Routine
Clear IFTX0(IFTX1)
=0
IFRX0(IFRX1)
=1
RX0(RX1) Interrupt
Routine
Clear IFRX0(IFRX1)
RETI
Figure 19-6 Software Flowchart of Shared Interrupt Vector
19.4 Multi Interrupt
If two interrupt requests of different priority level are received si-
multaneously, the request of higher priority level is serviced. If
interrupt requests of of equal priority level are received at the
same time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.
However, multiple processing through software for special fea-
tures is possible. Generally when an interrupt is accepted, the I-
flag is cleared to disable any further interrupt. But as user sets I-
flag in interrupt routine, some further interrupt can be serviced
even if certain interrupt is in progress. Refer to Figure 19-7.
Example: During Timer1 interrupt is in progress, INT0 interrupt
serviced without any suspend.
TIMER1: PUSH A
PUSH X
PUSH
LDM
LDM
EI
:
:
:
Y
IENH,#80H
IENL,#0
;Enable INT0 only
;Disable other int.
;Enable Interrupt
:
:
:
LDM
LDM
POP
POP
POP
RETI
IENH,#0FFH
IENL,#0FFH
Y
X
A
;Enable all interrupts
MAR. 2005 Ver 0.2
95