MC80F0424 Datasheet, PDF (95/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0424/0432/0448
The UART receive/transmit interrupt is generated by UART0IF
and UART1IF which are set by completion of UART data recep-
tion or transmission.
The SIO interrupt is generated by SIOIF which is set by comple-
tion of SIO data reception or transmission.
The interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW on Figure 8-3), the interrupt enable register
(IENH, IENL), and the interrupt request flags (in IRQH and
IRQL) except Power-on reset and software BRK interrupt. The
Table 19-1 shows the Interrupt priority.
Vector addresses are shown in Figure 8-6. Interrupt enable regis-
ters are shown in Figure 19-2. These registers are composed of in-
terrupt enable flags of each interrupt source and these flags
determines whether an interrupt will be accepted or not. When
enable flag is “0”, a corresponding interrupt source is prohibited.
Note that PSW contains also a master enable bit, I-flag, which
disables all interrupts at once.
Reset/Interrupt
Hardware Reset
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
UART0 Rx/Tx Interrupt
UART1 Rx/Tx Interrupt
Serial Input/Output
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
Timer/Counter 4
ADC Interrupt
Watchdog/Watch Timer
Basic Interval Timer
Symbol
RESET
INT0
INT1
INT2
INT3
UART0
UART1
SIO
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
ADC
WDT_WT
BIT
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Table 19-1 Interrupt Priority
R/W R/W R/W R/W R/W R/W R/W R/W
IENH INT0E INT1E INT2E INT3E ^{UART0E UART1E} SIOE T0E
MSB
LSB
ADDRESS: 0EA_H
INITIAL VALUE: 0000 0000_B
Timer/Counter 0 interrupt enable flag
Serial Communication interrupt enable flag
UART1 Tx/Rx interrupt enable flag
UART0 Tx/Rx interrupt enable flag
External interrupt 0 enable flag
External interrupt 1 enable flag
External interrupt 2 enable flag
External interrupt 3 enable flag
R/W
IENL T1E
MSB
R/W
T2E
R/W
T3E
R/W R/W R/W R/W R/W
T4E ADCE WDTE WTE BITE
LSB
ADDRESS: 0EB_H
INITIAL VALUE: 0000 0000_B
Basic Interval Timer interrupt enable flag
Watch timer interrupt enable flag
Watchdog timer interrupt enable flag
A/D Converter interrupt enable flag
Timer/Counter 4 interrupt enable flag
Timer/Counter 3 interrupt enable flag
Timer/Counter 2 interrupt enable flag
Timer/Counter 1 interrupt enable flag
Figure 19-2 Interrupt Enable Flag Register
MAR. 2005 Ver 0.2
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