MC80F0424 Datasheet, PDF (54/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0424/0432/0448
Preliminary
Source clock
BIT overflow
Binary-counter 1
WDTR
WDTIF interrupt
WDT reset
2
3
0
1
2
Counter
Clear
n
3
WDTR ← “1000_0011_B”
3
0
Counter
Clear
Match
Detect
reset
Figure 12-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is generated,
which drives the RESET pin low to reset the internal hardware.
The main clock oscillator also turns on when a watchdog timer
reset is generated in sub clock mode.
The IFWDT bit of IFR register is set when watchdog timer inter-
rupt is generated. (Refer to Figure 12-4)
IFR
-
MSB
R/W R/W R/W R/W R/W R/W
-
-
-
-
-
IFRX0 IFTX0 IFRX1 IFTX1 IFWT IFWDT
ADDRESS: 0DF_H
INITIAL VALUE: --00_0000_B
LSB
WDT interrupt occurred flag^NOTE1
WT interrupt occurred flag^NOTE1
UART1 Tx interrupt occurred flag^NOTE2
UART1 Rx interrupt occurred flag^NOTE2
UART0 Tx interrupt occurred flag^NOTE3
UART0 Rx interrupt occurred flag^NOTE3
NOTE1 : _{In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR}
in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and
Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after
reading this register.
NOTE2 : _{In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt}
service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
NOTE3 : _{In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt}
service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
Figure 12-4 IFR : Interrupt Flag Register
50
MAR. 2005 Ver 0.2