MC80F0424 Datasheet, PDF (96/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0424/0432/0448
Preliminary
R/W R/W R/W R/W R/W R/W R/W R/W
IRQH ^{INT0IF INT1IF INT2IF INT3IF UART0IF UART1IF SIOIF} T0IF
MSB
LSB
ADDRESS: 0EC_H
INITIAL VALUE: 0000 0000_B
Timer/Counter 0 interrupt request flag
Serial Communication interrupt request flag
UART1Tx/Rx interrupt request flag
UART0 Tx/Rx interrupt request flag
External interrupt 3 request flag
External interrupt 2 request flag
External interrupt 1 request flag
External interrupt 0 request flag
R/W
IRQL ^T1IF
MSB
R/W
T2IF
R/W
T3IF
R/W
T4IF
R/W R/W R/W R/W
ADCIF WDTIF WTIF BITIF
LSB
ADDRESS: 0ED_H
INITIAL VALUE: 0000 0000_B
Basic Interval Timer interrupt request flag
Watch timer interrupt request flag
Watchdog timer interrupt request flag
A/D Converter interrupt request flag
Timer/Counter 4 interrupt request flag
Timer/Counter 3 interrupt request flag
Timer/Counter 2 interrupt request flag
Timer/Counter 1 interrupt request flag
IFR
-
MSB
R/W R/W R/W R/W R/W R/W
- IFRX0 IFTX0 IFRX1 IFTX1 IFWT IFWDT
ADDRESS: 0DF_H
INITIAL VALUE: --00 0000_B
LSB
WDT interrupt occurred flag^NOTE1
WT interrupt occurred flag^NOTE1
UART1 Tx interrupt occurred flag^NOTE2
UART1 Rx interrupt occurred flag^NOTE2
UART0 Tx interrupt occurred flag^NOTE3
UART0 Rx interrupt occurred flag^NOTE3
NOTE1 : _{In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in}
interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch
timer is shared with interrupt vector address. These flag bits must be cleared by software after read-
ing this register.
NOTE2 : _{In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt}
service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
NOTE3 : _{In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt}
service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
Figure 19-3 Interrupt Request Flag Register
19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the
interrupt latch is cleared to “0” by a reset or an instruction. Inter-
rupt acceptance sequence requires 8 cycles of f_XIN (2µs at f_X-
IN^{=4MHz) after the completion of the current instruction}
execution. The interrupt service task is terminated upon execu-
tion of an interrupt return instruction [RETI].
92
MAR. 2005 Ver 0.2