MC80F0424 Datasheet, PDF (98/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0424/0432/0448
Preliminary
POP
Y
POP
X
POP
A
RETI
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
General-purpose register save/restore using push and pop instruc-
tions;
main task
acceptance of
interrupt
interrupt
service task
saving
registers
interrupt return
restoring
registers
19.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.
Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK inter-
rupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.
Each processing step is determined by B-flag as shown in Figure
19-5.
BRK or
TCALL0
B-FLAG
=1
BRK
INTERRUPT
ROUTINE
=0
TCALL0
ROUTINE
RETI
RET
19.3 Shared Interrupt Vector
In case of using interrupts of Watchdog Timer and Watch Timer
together, it is necessary to check IFR in interrupt service routine
to find out which interrupt is occurred, because the Watchdog
timer and Watch timer is shared with interrupt vector address.
These flag bits must be cleared by software after reading this reg-
ister.
In case of using interrupts of UART0 Tx and UART0 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART0 Tx and
Figure 19-5 Execution of BRK/TCALL0
UART0 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register.
In case of using interrupts of UART1 Tx and UART1 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART1 Tx and
UART1 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register. Each
processing step is determined by IFR as shown in Figure 19-6.
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MAR. 2005 Ver 0.2