MC80F0424 Datasheet, PDF (83/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0424/0432/0448
Serial I/O Mode Register(SIOM) controls serial I/O function. Ac-
cording to SCK1 and SCK0, the internal clock or external clock
can be selected.
Serial I/O Data Register(SIOR) is an 8-bit shift register. First
LSB is send or is received.
SIOM
R/W R/W R/W R/W R/W R/W R/W R
7
6
5
4
3
2
1
0
POL IOSW SM1 SM0 BSTCCKL1 SCK0 SIOST SIOSF
ADDRESS: 0E2_H
INITIAL VALUE: 0000 0001_B
Serial transmission status bit
0: Serial transmission is in progress
1: Serial transmission is completed
Serial transmission start bit
Setting this bit starts an Serial transmission.
After one cycle, bit is cleared to “0” by hardware.
Serial transmission Clock selection
00: f_XIN ÷ 4
01: f_XIN ÷ 16
10: TMR0OV(Timer0 Overflow)
11: External Clock
Serial transmission Operation Mode
00: Normal Port(R42,R43,R44)
01: Sending Mode(SCK,R43,SO)
10: Receiving Mode(SCK,SI,R44)
11: Sending & Receiving Mode(SCK,SI,SO)
Serial Input Pin Selection bit
0: SI Pin Selection
1: SO Pin Selection
SIOR
Serial Clock Polarity Selection bit
0: Data Transmission at Falling Edge
Received Data Latch at Rising Edge
1: Data Transmission at Rising Edge
Received Data Latch at Falling Edge
R/W R/W R/W R/W R/W R/W R/W R/W
76543210
BTCL
ADDRESS: 0E3_H
INITIAL VALUE: Undefined
Sending Data at Sending Mode
Receiving Data at Receiving Mode
Figure 16-2 SIO Control Register
16.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of SIOM)
to “1”. After one cycle of SCK, SIOST is cleared automatically
to “0”. At the default state of POL bit clear, the serial output data
from 8-bit shift register is output at falling edge of SCLK, and in-
put data is latched at rising edge of SCLK pin (Refer to Figure 16-
3). When transmission clock is counted 8 times, serial I/O counter
is cleared as ‘0”. Transmission clock is halted in “H” state and se-
rial I/O interrupt(SIOIF) occurred.
MAR. 2005 Ver 0.2
79