MC80F0424 Datasheet, PDF (50/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0424/0432/0448
Preliminary
11. BASIC INTERVAL TIMER
The MC80F0424/0432/0448 has one 8-bit Basic Interval Timer
that is free-run and can not stop. Block diagram is shown in Fig-
ure 11-1. In addition, the Basic Interval Timer generates the time
base for watchdog timer counting. It also provides a Basic inter-
val timer interrupt (BITIF).
The 8-bit Basic interval timer register (BITR) is increased every
internal count pulse which is divided by prescaler. Since prescal-
er has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024
of the oscillator frequency. As the count overflow from FFH to
00H, this overflow causes the interrupt to be generated. The Basic
Interval Timer is controlled by the clock control register
(CKCTLR) shown in Figure 10-2.
When write "1" to bit BTCL of CKCTLR, BITR register is
cleared to "0" and restart to count-up. The bit BTCL becomes "0"
after one machine cycle by hardware.
If the STOP instruction executed after writing "1" to bit RCWDT
of CKCTLR, it goes into the internal RC oscillated watchdog tim-
er mode. In this mode, all of the block is halted except the internal
RC oscillator, Basic Interval Timer and RC Watchdog Timer.
More detail informations are explained in Power Saving Func-
tion. The bit WDTON decides Watchdog Timer or the normal 7-
bit timer.
Source clock can be selected by lower 3 bits of CKCTLR.
BITR and CKCTLR are located at same address, and address
0F2_H is read as a BITR, and written to CKCTLR.
X_IN PIN
Internal RC OSC
RCWDT
÷8
÷16
÷32
÷64
÷128
÷256
÷512
÷1024
MUX
Select Input clock ³
BTS[2:0]
[0F2_H]
Basic Interval Timer
clock control register
8-bit up-counter
1 source
clock
overflow
BITR
BITIF
0
[0F2_H]
clear
RCWDT
CKCTLR
BTCL
Read
Internal bus line
Basic Interval
Timer Interrupt
Watchdog timer
0
(WDTCK)
1
RCWDT
Figure 11-1 Block Diagram of Basic Interval Timer
CKCTLR
[2:0]
000
001
010
011
100
101
110
111
Source clock
f_XIN÷8
f_XIN÷16
f_XIN÷32
f_XIN÷64
f_XIN÷128
f_XIN÷256
f_XIN÷512
f_XIN÷1024
Interrupt (overflow) Period (ms)
@ f_XIN = 8MHz
0.256
0.512
1.024
2.048
4.096
8.192
16.384
32.768
Table 11-1 Basic Interval Timer Interrupt Period
46
MAR. 2005 Ver 0.2