MC80F0424 Datasheet, PDF (48/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0424/0432/0448
Preliminary
10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generator produces the basic
clock pulses which provide the system clock to be supplied to the
CPU and the peripheral hardware. It contains two oscillators
which are main-frequency clock oscillator and a sub-frequency
clock oscillator. The system clock operation can be easily ob-
tained by attaching a crystal or a ceramic resonator between the
X_IN and X_OUT pin and the SX_IN and SX_OUT pin, respectively.
The system clock can also be obtained from the external oscilla-
tor. In this case, it is necessary to input a external clock signal to
the X_IN pin and open the X_OUT pin. There are no requirements on
the duty cycle of the external clock signal, since the input to the
internal clocking circuitry is through a divide-by-two flip-flop,
but minimum and maximum high and low times specified on the
data sheet must be observed.
The internal system clock can be selected by bit0 and bit1 of the
system clock control register (SCMR). The registers are shown in
Figure 10-2. In case of selecting sub clock, to oscillate or stop the
main clock is decided by MCC bit (SCMR.2).
On the initial reset, internal system clock is PS1 which is the fast-
est and other clock can be provided by bit0 and bit1 of SCMR.
The clock among the not-divided original clock and clocks divid-
ed by 1, 2, 4,..., up to 4096 can be provided to the peripheral
block, Peripheral clock is enabled or disabled by STOP instruc-
tion. The peripheral clock is controlled by clock control register
(CKCTLR). See "11. BASIC INTERVAL TIMER" on page 46
for details.
The subclock oscillation connected to SXIN and SXOUT pin is
enabled by the set of corresponding XTEN bit of PSR1 register
(See Figure 10-3).
STOP
MCC
X_IN
X_OUT
SX_IN
SX_OUT
Main OSC
Stop
CS1 CS0
OSC
Circuit
Sub OSC
Circuit
MUX
SLEEP
f_EX
Clock Pulse
Generator
(÷2)
Internal
system clock
Sub OSC
Run
XTEN
(PSR1 reg.)
*MCC, CS1, CS0 are described
in next figure.
PRESCALER
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
÷1 ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096
Peripheral clock
f_EX (Hz)
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10 PS11 PS12
Frequency 4M
2M
1M
4M
period
250n 500n
1u
500K
2u
250K
4u
125K
8u
62.5K 31.25K 15.63K 7.183K 3.906K
16u
32u
64u 128u 256u
1.953K 976
512u 1.024m
Figure 10-1 Block Diagram of Clock Generator
44
MAR. 2005 Ver 0.2