MC80F0424 Datasheet, PDF (114/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0424/0432/0448
Preliminary
23. RESET
The MC80F0424/0432/0448 have four types of reset generation
procedures; they are an external reset input, a watch-dog timer re-
set, power fail processor reset, and address fail reset. Table 23-1
shows on-chip hardware initialization by reset action.
On-chip Hardware
Program counter
(PC)
RAM page register
G-flag
Operation mode
(RPR)
(G)
Initial Value
(FFFF_H) - (FFFE_H)
0
0
Main-frequency clock
On-chip Hardware
Peripheral clock
Watchdog timer
Control registers
Power fail detector
Initial Value
Off
Disable
Refer to Table 8-1
Disable
Table 23-1 Initializing Internal Status by Reset Action
External Reset Input
The reset input is the RESET pin, which is the input to a Schmitt
Trigger. A reset in accomplished by holding the RESET pin low
for at least 8 oscillator periods, within the operating voltage range
and oscillation stable, it is applied, and the internal state is initial-
ized. After reset, 65.5ms (at 4 MHz) add with 7 oscillator periods
are required to start execution as shown in Figure 23-2.
Internal RAM is not affected by reset. When V_DD is turned on,
the RAM content is indeterminate. Therefore, this RAM should
be initialized before read or tested it.
When the RESET pin input goes to high, the reset operation is re-
leased and the program execution starts at the vector address
stored at addresses FFFE_H - FFFF_H.
A connection for simple power-on-reset is shown in Figure 23-1.
V_CC
7036P
10kΩ
+
10uF
to the RESET pin
Figure 23-1 Simple Power-on-Reset Circuit
Oscillator
(X_IN pin)
RESET
1234567
ADDRESS
BUS
?
??
?
FFFE FFFF Start
DATA
BUS
?
? ? ? FE ADL ADH OP
Stabilization Time
t_ST =65.5mS at 4MHz
Reset Process Step
1
t_ST = _{fXIN ÷1024} x 256
Figure 23-2 Timing Diagram after Reset
MAIN PROGRAM
Address Fail Reset
The Address Fail Reset is the function to reset the system by
checking code access of abnormal and unwished address caused
by erroneous program code itself or external noise, which could
not be returned to normal operation and would become malfunc-
tion state. If the CPU tries to fetch the instruction from ineffective
code area or RAM area, the address fail reset is occurred. Please
refer to Figure 11-2 for setting address fail option.
110
MAR. 2005 Ver 0.2