MC80F0424 Datasheet, PDF (91/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0424/0432/0448
17.5 Communication operation
The transmit operation is enabled when bit 7 (TXE) of the asyn-
chronous serial interface mode register (ASIMR/ASIMR1) is set
to 1. The transmit operation is started when transmit data is writ-
ten to the transmit shift register (TXR/TXR1). The timing of the
transmit completion interrupt request is shown in Figure 17-3.
The receive operation is enabled when bit 6 (RXE) of the asyn-
chronous serial interface mode register (ASIMR/ASIMR1) is set
to 1, and input via the RxD0/RxD1 pin is sampled. The serial
clock specified by ASIMR/ASIMR1 is used to sample the RxD0/
RxD1 pin. Once reception of one data frame is completed, a re-
ceive completion interrupt request (UART0IF/UART1IF) oc-
curs. Even if an error has occurred, the receive data in which the
error occurred is still transferred to RXR/RXR1. When ASIMR
bit 1 (ISRM) is cleared to 0 upon occurrence of an error, UART0/
UART1 interrupt occurs. When ISRM bit is set to 1, UART0/
UART1 interrupt does not occur in case of error occurrence. Fig-
ure 17-3 shows the timing of the asynchronous serial interface re-
ceive completion interrupt request.
In case of using interrupts of UART0 Tx and UART0 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART0 Tx and
UART0 Rx is shared with interrupt vector address.
In case of using interrupts of UART1 Tx and UART1 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART1 Tx and
UART1 Rx is shared with interrupt vector address.
These flag bits must be cleared by software after reading this reg-
ister. These flag bits must be cleared by software after reading
this register. Each processing step is determined by IFR as shown
in Figure 17-1.
UART0(UART1)
Interrupt Request
IFTX0(IFTX1)
=0
=1
TX0(TX1) Interrupt
Routine
Clear IFTX0(IFTX1)
=0
IFRX0(IFRX1)
=1
RX0(RX1) Interrupt
Routine
Clear IFRX0(IFRX1)
RETI
Figure 17-1 Shared Interrupt Vector of UART
MAR. 2005 Ver 0.2
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