MC80F0424 Datasheet, PDF (102/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0424/0432/0448
Preliminary
20. OPERATION MODE
The system clock controller starts or stops the main-frequency
clock oscillator and switches between the main and sub frequency
clock. The operating mode is generally divided into the main ac-
tive mode, the sub active mode 1 and sub active mode 2, which
are controlled by System clock control register (SCMR). Figure
20-1 shows the operating mode transition diagram.
System clock control is performed by the system clock mode reg-
ister, SCMR. During reset, this register is initialized to “0” so that
the main-clock operating mode is selected.
Main Active mode
This mode is fast-frequency operating mode. The CPU and the
peripheral hardware are operated on the high-frequency clock. At
reset release, this mode is invoked.
Sub Active mode
This mode is low-frequency operating mode. In this mode, the
CPU and the peripheral hardware clock are provided by low-fre-
quency clock oscillation, so power consumption can be reduced.
SLEEP mode
In this mode, the CPU clock stops while peripherals and the os-
cillation source continues to operate normally.
STOP mode
In this mode, the system operations are all stopped, holding the
internal states valid immediately before the stop at the low power
consumption level. The main oscillation source stops, but the sub
clock oscillation and watch timer by sub clock and RC-oscillated
watchdog timer don’t stop.
Main : Oscillation
Sub : Oscillation or stop
System Clock : Main
Main : Oscillation
Sub : Oscillation
System Clock : Sub
Main Active
Mode
LDM SCMR, #02H
* _Note3
LDM SCMR, #01H
* ^{Note1 / Note2}
* ^Note4
Sub Active
Mode 1
Stop / Sleep
Mode
LDM
SCMR,#06H
* Note1 / Note2
* Note4
Stop : System Clock Oscillation stop
Sleep : System Clock Oscillation run
(CPU stops, Peripherals operate)
Sub Active
Mode 2
Main : Stop
Sub : Oscillation
System Clock : Sub
* Note1 : Stop released by Reset,
Watch Timer, Watchdog Timer
Timer(event counter),
SIO (External clock), UART
External interrupt
* Note2 : Sleep released by
Reset, or All interrupts
* Note3 : List of instruction is
CLR1 SCMR.2 ;Main OSC ON
NOP ;for Oscillation stabilization time
NOP ;for Oscillation stabilization time
LDM SCMR, #01H
* Note4 :
1) Stop mode Admission
LDM SSCR, #5AH
STOP
NOP
NOP
2) Sleep mode Admission
LDM SSCR, #0FH
- Sub clock cannot be stopped by STOP instruction.
Figure 20-1 Operating Mode
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MAR. 2005 Ver 0.2