MC80F0424 Datasheet, PDF (29/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0424/0432/0448
PSW
NEGATIVE FLAG
OVERFLOW FLAG
SELECT DIRECT PAGE
when G=1, page is selected to “page 1”
BRK FLAG
MSB
LSB
N V G B H I Z C RESET VALUE: 00_H
CARRY FLAG RECEIVES
CARRY OUT
ZERO FLAG
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt caused
by Reset or software BRK instruction. All interrupts are disabled
when cleared to “0”. This flag immediately becomes “0” when an
interrupt is served. It is set by the EI instruction and cleared by
the DI instruction.
This flag assigns RAM page for direct addressing mode. In the di-
rect addressing mode, addressing area is from zero page 00_H to
0FF_H when this flag is "0". If it is set to "1", addressing area is
assigned 100_H to 1FF_H. It is set by SETG instruction and cleared
by CLRG.
[Overflow flag V]
[Half carry flag H]
After operation, this is set when there is a carry from bit 3 of ALU
or there is no borrow from bit 4 of ALU. This bit can not be set
or cleared except CLRV instruction with Overflow flag (V).
[Break flag B]
This flag is set to “1” when an overflow occurs as the result of an
arithmetic operation involving signs. An overflow occurs when
the result of an addition or subtraction exceeds +127(7F_H) or -
128(80_H). The CLRV instruction clears the overflow flag. There
is no set instruction. When the BIT instruction is executed, bit 6
of memory is copied to this flag.
This flag is set by software BRK instruction to distinguish BRK
from TCALL instruction with the same vector address.
[Direct page flag G]
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of
a data or arithmetic operation. When the BIT instruction is exe-
cuted, bit 7 of memory is copied to this flag.
MAR. 2005 Ver 0.2
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