MC80F0424 Datasheet, PDF (101/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0424/0432/0448
Response Time
The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF at every
machine cycle. The values are not actually polled by the circuitry
until the next machine cycle. If a request is active and conditions
are right for it to be acknowledged, a hardware subroutine call to
the requested service routine will be the next instruction to be ex-
ecuted. The DIV itself takes twelve cycles. Thus, a minimum of
twelve complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution of the
first instruction of the service routine.
Figure 19-9 shows interrupt response timings.
max. 12 f_XIN
8 f_XIN
Interrupt Interrupt
goes latched
active
Interrupt
processing
Interrupt
routine
Figure 19-9 Interrupt Response Timing Diagram
IEDS
MSB
LSB
W
W
W
W
W
W
W
W
IED3H IED3L IED2H IED2L IBETDC1LH IED1L IED0H IED0L
INT3
INT2
INT1
INT0
Edge selection register
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)
ADDRESS: 0EE_H
INITIAL VALUE: 00_H
W
W
W
PSR0
PWM3O PWM1O EC1E
MSB
0: R54
1: PWM3O
W
W
EC0E IBNTTC3LE
W
INT2E
W
W
INT1E INT0E
LSB
ADDRESS: 0F8_H
INITIAL VALUE: 00_H
0: R10
1: INT0
0: R53
1: PWM1O
0: R11
1: INT1
0: R51
1: EC1
0: R15
1: EC0
0: R12
1: INT2
0: R50
1: INT3
Figure 19-10 IEDS register and Port Selection Register PSR0
MAR. 2005 Ver 0.2
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