MC80F0424 Datasheet, PDF(88/135 Page) List of Unclassifed Manufacturers

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MC80F0424 Datasheet, PDF (88/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

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MC80F0424/0432/0448

Preliminary

Asynchronous serial interface mode register

(ASIMR)

This is an 8 bit register that controls UART serial transfer opera-

tion. ASIMR is set by a 1 bit or 8 bit memory manipulation in-

truction. The RESET input sets ASIMR to 0000_-00-B. Table 17-

2 shows the format of ASIMR.

ASIMR / TXE RXE PS1 PS0

ASIMR1

Address : 0E6H / EE6H

Reset value : 0000-00-B

- SL ISRM

TXE RXE Operation Mode RxD Pin Func.

0 0 Operation stop Port function(R46)

0 1 UART mode Serial function

(Receive only)

(RxD0)

TxD Pin Func.

Port

function(R47)

1 0 UART mode

Port function

(Transmit only)

(R46)

Serial function

(TxD0)

1 1 UART mode Serial function

( RX & TX )

(RxD0)

PS1 PS0

Parity Bit Specification

0 0 No parity

0 1 Zero parity always added during transmission.

No parity detection during reception (parity errors do not

occur)

1 0 Odd parity

1 1 Even parity

0 1 bit

1 2 bit

Stop Bit Length for Specification for Transmit Data

ISRM Receive interrupt request is issued when an error occurs

0 Receive Completion Interrupt Control When Error Occurs

1 Receive completion interrupt request is not issued when an error

occurs

Table 17-2 Asynchronous Serial Interface Mode

Note: Do not switch the operation mode until the current

serial transmit/receive operation has stopped.

Asynchronous serial interface status register

(ASISR)

When a receive error occurs during UART mode, this register in-

dicates the type of error. ASISR can be read by an 8 bit memory

manipulation instruction. The RESET input sets ASISR to -----

000B. Table 17-3 shows the format of ASISR.

Address : 0E7H / EE7H

Reset value : -----000B

ASISR /

ASISR1

- PE FE OVE

Parity Error Flag

0 No parity error

1 Parity error (Transmit data parity not matched)

Frame Error Flag

0 No Frame error

1 Framing errorNote1 (stop bit not detected)

OVE

Overrun Error Flag

0 No overrun error

1 Overrun errorNote2

(Next receive operation was completed before data was read

from receive buffer register (RXR)

Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in

ASIMR, stop bit detection during a recive operation only applies

to a stop bit length of 1bit.

2. Be sure to read the contents of the receive buffer register(RXR)

when an overrun error has occurred.

Until the contents of RXR are read, futher overrun errors will

occur when receiving data.

Table 17-3 Asynchronous Serial Interface Status

Baud rate generator control register (BRGCR)

This register sets the serial clock for serial interface. BRGCR is

set by an 8 bit memory manipulation instruction. The RESET in-

put sets BRGCR to -001_0000B.

Table 17-4 shows the format of BRGCR.

MAR. 2005 Ver 0.2

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