MC80F0424 Datasheet, PDF (89/135 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0424/0432/0448
BRGCR /
BRGCR1
Address : 0E8H / EE8H
Reset value : -0010000B
- TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
TPS2 TPS1 TPS0 Source Clock Selection for 5 Bit count n
MDL3 MDL2 MDL1 MDL0
Input Clock Selection k
0
0
0 ACLK0 / ACLK1
0
0
0
0
0
f_SCK / 16
0
0
0
1
f_XIN / 2
0
1
0
f_XIN / 4
1
0
0
0
1
f_SCK / 17
1
2
0
0
1
0
f_SCK / 18
2
0
1
1
f_XIN / 8
1
0
0
f_XIN / 16
3
0
0
1
1
f_SCK / 19
3
4
0
1
0
0
f_SCK / 20
4
1
0
1
f_XIN / 32
5
0
1
0
1
f_SCK / 21
5
1
1
0
f_XIN / 64
1
1
1
f_XIN / 128
6
0
1
1
0
f_SCK / 22
6
7
0
1
1
1
f_SCK / 23
7
1
0
0
0
f_SCK / 24
8
1
0
0
1
f_SCK / 25
9
Caution Writing to BRGCR/BRGXR1 during a communication operation may
1
0
1
0
f_SCK / 26
10
cause abnormal output from the baud rate generator and
disable further communication operations. Therefore, do not
1
0
1
1
f_SCK / 27
11
write to BRGCR/BRGCR1 during a communication operation.
1
1
0
0
f_SCK / 28
12
Remarks 1. f_SCK : Source clock for 5 bit counter
2. n : Value set via TPS0 to TPS2 ( 0 ≤ n ≤ 7 )
3. k : Source clock for 5 bit counter ( 0 ≤ k ≤ 14 )
1
1
0
1
f_SCK / 29
13
1
1
1
0
f_SCK / 30
14
1
1
1
1 Setting prohibited
-
Table 17-4 Baud Rate Generator Control Register (BRGCR / BRGCR1) Format
17.3 Communication operation
TxD
RxD
TX
INTERRUPT
RX
INTERRUPT
1 data frame
Start _{D0 D1 D2 D3 D4 D5 D6 D7} Parity Stop
character bits
1 data frame consists of following bits.
- Start bit : 1 bit
- Character bits : 8 bits
- Parity bit : Even parity, Odd parity, Zero parity, No parity
- Stop bit(s) : 1 bit or 2 bits
(In case of 1 stop bit)
(In case of 1 stop bit)
Figure 17-3 UART data format and interrupt timing diagram
The transmit operation is enabled when bit 7 (TXE) of the asyn-
chronous serial interface mode register (ASIMR/ASIMR1) is set
to 1. The transmit operation is started when transmit data is writ-
ten to the transmit shift register (TXR). The timing of the transmit
completion interrupt request is shown in Figure 17-3.
The receive operation is enabled when bit 6 (RXE) of the asyn-
chronous serial interface mode register (ASIMR/ASIMR1) is set
to 1, and input via the RxD0 pin is sampled. The serial clock spec-
ified by ASIMR/ASIMR1 is used to sample the RxD0/RxD1 pin.
Once reception of one data frame is completed, a receive comple-
tion interrupt request (UART0IF/UART1IF) occurs. Even if an
error has occurred, the receive data in which the error occurred is
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