C8051F326 Datasheet, PDF (83/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
11.1. Port I/O Initialization
Port I/O initialization consists of the following steps:
Step 1. Select if the port pin will be used as an output or input.
Step 2. If output, select the output mode: open-drain or push-pull.
Step 3. Configure the PnMDOUT and Pn latches according to the desired input or output
configuration.
Step 4. Select if /SYSCLK will appear on the P0.0 output and configure GPIOCN.0.
Step 5. Enable Global Inputs (INPUTEN = ‘1).
Port pins can be used as digital inputs or outputs. To configure a Port pin as a digital input, write ‘0’ to the
corresponding bit in register PnMDOUT, and write ‘1’ to the corresponding Port latch (register Pn). When a
Port pin is read, the actual voltage at the pin is used to determine a logic 0 or logic 1 value; the Port latch is
write-only.
Digital output pins can be configured to open-drain or push-pull. In open drain mode (corresponding bit in
PnMDOUT is set to ‘0’), the low output driver is turned on when the Port latch is a logic 0 and turned off
when the Port latch is a logic 1. The high output driver is always off, regardless of the Port latch setting. In
open drain mode, an output port pin becomes a high impedance input when the Port latch is a logic 1. An
external pullup resistor is recommended if the pin is intended for use as an output. This mode is useful
when interfacing to 5V logic.
Each port pin has an internal weak pullup that is enabled when the WEAKPUD bit ‘0’, the port output mode
is configured as open-drain, and the port latch is a logic 1 (pin is a high impedance input). The weak pullup
is disabled if the pin is configured to push-pull mode or the Port latch is a logic 0 to avoid unnecessary
power dissipation.
In push-pull mode (corresponding bit in PnMDOUT is set to ‘1’), one of the output drivers will always
remain on. When the Port latch is a logic 0, the low output driver is turned on and the high output driver is
off. When the Port latch is a logic 1, the low output driver is turned off and the high output driver is turned
on. Note that in push-pull mode, the voltage at the port pin will reflect the logic level of the output Port latch.
This mode cannot be used to drive logic levels higher than VIO or VDD.
After each port pin is properly configured as an input or output, special signals can be routed to select port
pins. Special signals include /SYSCLK on P0.0, XTAL2 clock input on P0.3, UART TX on P0.4, and UART
RX on P0.5. The /SYSCLK signal can be routed to P0.0 by setting GPIOCN.0 to ‘1’. The XTAL2 clock input
is always routed to P0.3. The UART TX signal is always enabled, and ANDed with the P0.4 latch. When
using the UART, the P0.4 Port latches should be logic ‘1’ to allow the UART to control the TX pin. If the Port
latch is written ‘0’ at any time, the TX signal will be forced to a logic 0. When the UART is not used, the
value of the TX signal is parked at logic 1 and P0.4 can be used as GPIO.
Important Note: Setting the INPUTEN bit in GPIOCN to ‘1’ globally enables digital inputs. Until global
inputs are enabled, all port pins on the device remain as output only and cannot be used to sense the logic
level on the port pin. INPUTEN must be set to ‘1’ in order to use UART RX, XTAL2, or the /INT0 input.
11.2. General Purpose Port I/O
Port0, Port2, and Port3 are accessed through corresponding special function registers (SFRs) that are
both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched
to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are
returned if INPUTEN is set to ‘1’. The exception to this is the execution of the read-modify-write instruc-
tions. The read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL,
JBC, CPL, INC, DEC, and DJNZ. The MOV, CLR and SETB instructions are also read-modify-write when
the destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the
pin) is read, modified, and written back to the SFR.
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