C8051F326 Datasheet, PDF (104/140 Pages) List of Unclassifed Manufacturers – Full Speed USB, 16 kB Flash MCU Family

C8051F326/7
USB Register Definition 12.13. CMINT: USB0 Common Interrupt
R
R
R
R
R
R
R
R
Reset Value
—
—
—
—
SOF RSTINT RSUINT SUSINT 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 USB Address:
0x06
Bits7–4:
Bit3:
Bit2:
Bit1:
Bit0:
Unused. Read = 0000b; Write = don’t care.
SOF: Start of Frame Interrupt
Set by hardware when a SOF token is received. This interrupt event is synthesized by hard-
ware: an interrupt will be generated when hardware expects to receive a SOF event, even if
the actual SOF signal is missed or corrupted.
This bit is cleared when software reads the CMINT register.
0: SOF interrupt inactive.
1: SOF interrupt active.
RSTINT: Reset Interrupt-pending Flag
Set by hardware when Reset signaling is detected on the bus.
This bit is cleared when software reads the CMINT register.
0: Reset interrupt inactive.
1: Reset interrupt active.
RSUINT: Resume Interrupt-pending Flag
Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend
mode.
This bit is cleared when software reads the CMINT register.
0: Resume interrupt inactive.
1: Resume interrupt active.
SUSINT: Suspend Interrupt-pending Flag
When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hard-
ware when Suspend signaling is detected on the bus. This bit is cleared when software
reads the CMINT register.
0: Suspend interrupt inactive.
1: Suspend interrupt active.
USB Register Definition 12.14. IN1IE: USB0 IN Endpoint Interrupt Enable
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits7–2:
Bit1:
Bit0:
Unused. Read = 000000b. Write = don’t care.
IN1E: IN Endpoint 1 Interrupt Enable
0: IN Endpoint 1 interrupt disabled.
1: IN Endpoint 1 interrupt enabled.
EP0E: Endpoint 0 Interrupt Enable
0: Endpoint 0 interrupt disabled.
1: Endpoint 0 interrupt enabled.
R/W
IN1E
Bit1
R/W
EP0E
Bit0
Reset Value
00000011
USB Address:
0x07
104
Rev. 0.5